Lateral super-junction MOSFET device and termination structure

• US 9,312,381 B1
• Filed: 06/23/2015
• Issued: 04/12/2016
• Est. Priority Date: 06/23/2015
• Status: Active Grant

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Bobde, Madhur, Guan, Lingpeng, Padmanabhan, Karthik, Yilmaz, Hamza
• Primary Examiner(s): Thai, Luan C
• Application Number:
  US14/747,925
• Time in Patent Office: 294 Days
• Field of Search: 257/339
• US Class Current: 1/1
• CPC Class Codes: H01L 29/063 Reduced surface field [RESURF] pn-junction structures
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0865 Disposition
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/0882 Disposition
• CPC Class Codes: H01L 29/1079 with insulated gate
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/404 Multiple field plate structures
• CPC Class Codes: H01L 29/405 Resistive arrangements, e.g. resistive or semi-insulating field plates
• CPC Class Codes: H01L 29/4175 for lateral devices where the connection to the source or drain region is done through at least one part of the semiconductor substrate thickness, e.g. with connecting sink or with via-hole
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/66681 Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7809 having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7816 Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/7823 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402

Abstract

A lateral superjunction MOSFET device includes a gate structure, a first column connected to the lateral superjunction structure and a second column disposed in close proximity to the first column. The lateral superjunction MOSFET device includes the first column to receive current from the channel when the MOSFET is turned on and to distribute the channel current to the lateral superjunction structure functioning as the drain drift region. The second column disposed near the first column is used to pinch off the first column when the MOSFET device is to be turned off and to block the high voltage being sustained by the MOSFET device at the drain terminal from reaching the gate structure. In some embodiments, the lateral superjunction MOSFET device further includes termination structures for the drain, source and body contact doped region fingers.

Claims

1. A lateral superjunction MOSFET device, comprising:

a semiconductor base layer comprising a heavily doped semiconductor substrate of a first conductivity type and a lightly doped semiconductor layer of the first conductivity type formed on the substrate, the substrate forming a bottom source electrode of the MOSFET device;

a semiconductor body formed on the semiconductor base layer and comprising a lateral superjunction structure including a plurality of alternating N-type and P-type thin semiconductor regions formed substantially in parallel with a major surface of the semiconductor body, the alternating N-type and P-type thin semiconductor regions forming a drain drift region of the MOSFET device;

a body region of the first conductivity type formed in a first surface of the semiconductor body, the first surface being opposite the semiconductor base layer;

a conductive gate formed on the semiconductor body at a near end of the lateral superjunction structure and insulated from the semiconductor body by a gate dielectric layer;

a source region of a second conductivity type, opposite the first conductivity type, formed in the body region and formed self-aligned with a first end of the conductive gate, the source region extending under the first end of the conductive gate to form a small overlap;

a body contact region of the first conductivity type formed in the body region and adjacent to the source region;

a drain region of the second conductivity type formed at a distant end of the lateral superjunction structure, the drain region extending through the lateral superjunction structure;

a first column of the second conductivity type formed under the conductive gate and spaced apart from the source region, the region of the semiconductor body under the conductive gate between the source region and the first column forming a channel of the MOSFET device, the first column extending through the lateral superjunction structure and is electrically unbiased; and

a second column of the first conductivity type formed under and in electrical contact with the body contact region, the second column extending through the lateral superjunction structure,

wherein the first column distributes a current from the channel of the MOSFET device in an on-state to the drain drift region formed by the lateral superjunction structure to be collected by the drain region, and the second column pinches off the first column in an off-state of the MOSFET device to isolate the conductive gate from a drain voltage at the drain region.

2. The lateral superjunction MOSFET device of claim 1, further comprising:

a buried region of the second conductivity type formed on the semiconductor base layer and under the drain region.

3. The lateral superjunction MOSFET device of claim 1, wherein the conductive gate comprises a low voltage gate sustaining a voltage much less than the drain voltage sustained by the drain region.

4. The lateral superjunction MOSFET device of claim 1, wherein the thin semiconductor regions of the second conductivity type in the lateral superjunction structure form drain current paths to carry the drain drift current in the on-state of the MOSFET device from the channel to is the drain region;

and the thin semiconductor regions of the second conductivity type form charge-balanced partition region to block the drain current paths in the off-state of the MOSFET device.

5. The lateral superjunction MOSFET device of claim 1, wherein the thin semiconductor regions of the second conductivity type is formed around the second column.

6. The lateral superjunction MOSFET device of claim 1, wherein the conductive gate, the source region and the first column are arranged so that the current flowing under the gate in the channel of the MOSFET device flows parallel to the drain drift region.

7. The lateral superjunction MOSFET device of claim 6, wherein the second column comprises a plurality of blocking columns of the first conductivity formed spaced apart along the body contact region and extend in a direction perpendicular to the drain drift region, each blocking column extending through the lateral superjunction structure.

8. The lateral superjunction MOSFET device of claim 1, wherein the conductive gate, the source region and the first column are arranged so that the current flowing under the gate in the channel of the MOSFET device flows perpendicular to the drain drift region.

9. The lateral superjunction MOSFET device of claim 8, wherein the second column comprises a plurality of blocking columns of the first conductivity formed spaced apart on either side of the conductive gate and in alignment with the conductive gate in a direction perpendicular to the drain drift region.

10. The lateral superjunction MOSFET device of claim 1, wherein the drain region, the source region and the body contact region each comprises a doped region finger formed in the semiconductor body, the doped region finger having a termination region at an end of the doped region finger, the lateral superjunction MOSFET device further comprising a termination structure formed in the termination region of each doped region finger and including one or more termination columns having the same conductivity type as the doped region finger and positioned near the end of the doped region finger, the one or more termination column extending through the lateral superjunction structure and being electrically unbiased.

11. The lateral superjunction MOSFET device of claim 10, wherein the one or more termination columns comprise a one-dimensional array of termination columns extending in a direction away from the end of the doped region finger.

12. The lateral superjunction MOSFET device of claim 10, wherein the one or more termination columns forming a two-dimensional array of termination columns arranged at the end of the doped region finger and having a pattern selected to optimize a breakdown characteristic of the MOSFET device.

13. The lateral superjunction MOSFET device of claim 10, wherein the termination structure further comprises a conductive field plate formed on the semiconductor body and surrounding a termination column.

14. The lateral superjunction MOSFET device of claim 13, wherein the conductive field plate comprises a multi-step field plate including a conductive field plate as a first step and a dielectric field plate in subsequent steps.

15. The lateral superjunction MOSFET device of claim 13, wherein the conductive field plate comprises a polysilicon field plate.

16. The lateral superjunction MOSFET device of claim 10, wherein the termination structure further comprises a reduced surface field shallow implant region having the same conductivity is type as the doped region finger and positioned near the end of the doped region finger, the reduced surface field shallow implant region having a shape selected to optimize a field shaping effect for the MOSFET device.

17. The lateral superjunction MOSFET device of claim 16, wherein the reduced surface field shallow implant region has a triangular shape or a rectangular shape.

18. The lateral superjunction MOSFET device of claim 1, wherein the first conductivity type comprises P-type conductivity and the second conductivity type comprises N-type conductivity.

19. The lateral superjunction MOSFET device of claim 1, wherein the source region, the drain region and the body contact region comprise heavily doped regions of the respective conductivity type.

20. The lateral superjunction MOSFET device of claim 1, wherein the first column and the second column comprise vertical doped regions formed in the semiconductor body.