Single photon avalanche diode imaging sensor for complementary metal oxide semiconductor stacked chip applications

• US 9,312,401 B2
• Filed: 01/15/2014
• Issued: 04/12/2016
• Est. Priority Date: 01/15/2014
• Status: Active Grant

• Current Assignee: Omnivision Technologies Incorporated (Will Semiconductor Co., Ltd. Shanghai)
• Original Assignee: Omnivision Technologies Incorporated (Will Semiconductor Co., Ltd. Shanghai)
• Inventors: Webster, Eric A. G.
• Primary Examiner(s): Bui Pho, Pascal M
• Application Number:
  US14/155,848
• Publication Number:
  US 20150200222A1
• Time in Patent Office: 818 Days
• Field of Search: 250/208.1, 250/216, 250/214.R, 250/214.1, 250/214.DC, 348272-283, 348294-324, 348/332, 348/333.08, 348335-338, 257/233, 257291-294, 257/414, 257431-466
• US Class Current: 1/1
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 27/1463 Pixel isolation structures
• CPC Class Codes: H01L 27/14634 Assemblies, i.e. Hybrid structures
• CPC Class Codes: H01L 27/14636 Interconnect structures
• CPC Class Codes: H01L 31/02027 for devices working in avalanche mode
• CPC Class Codes: H01L 31/107 the potential barrier working in avalanche mode, e.g. avalanche photodiodes

Abstract

An imaging sensor system includes a single photon avalanche diode (SPAD) imaging array including N pixels formed in a first semiconductor layer of a first wafer. Substantially an entire thickness of the first semiconductor layer of each pixel is fully depleted such that a multiplication region included in each pixel near a front side is configured to be illuminated with photons through a back side and through the substantially entire thickness of the fully depleted first semiconductor layer. Deep n type isolation regions are disposed in the first semiconductor layer between the pixels to isolate the pixels. N digital counters are formed in a second semiconductor layer of a second wafer that is bonded to the first wafer. Each of the N digital counters is coupled to the SPAD imaging array and coupled to count output pulses generated by a respective one of the pixels.

Claims

1. An imaging sensor system, comprising:

a first semiconductor layer of a first wafer;

a single photon avalanche diode (SPAD) imaging array including a plurality of pixels formed in the first semiconductor layer, wherein the plurality of pixels include an N number of pixels, wherein substantially an entire thickness of the first semiconductor layer of each pixel is fully depleted such that a multiplication region included in each pixel near a front side of the first semiconductor layer is configured to be illuminated with photons through a back side of the first semiconductor layer and through the substantially entire thickness of the fully depleted first semiconductor layer;

deep n type isolation regions disposed in the first semiconductor layer between the pixels to isolate each one of the plurality of pixels from one another;

a second semiconductor layer of a second wafer bonded to the first wafer;

a plurality of digital counters formed in the second semiconductor layer and electrically coupled to the SPAD imaging array, wherein the plurality of digital counters includes at least N number of digital counters, wherein each of the N number of digital counters are coupled to count output pulses generated by a respective one of the plurality of pixels.

2. The imaging sensor system of claim 1 wherein each of the plurality of digital counters formed in the second semiconductor layer comprises a separate complementary metal oxide semiconductor (CMOS) circuit disposed in the second semiconductor layer of the second wafer.

3. The imaging sensor system of claim 1 further comprising a p+ doped region disposed on the back side of the first semiconductor layer.

4. The imaging sensor system of claim 1 wherein each of the N number of digital counters is coupled the respective one of the plurality of pixels through separate connections to respective terminals of the respective SPAD regions of the pixels.

5. The imaging sensor system of claim 1 further comprising:

a first interconnect layer disposed on the front side of the first semiconductor layer; and

a second interconnect layer disposed on the second semiconductor layer, wherein the first wafer is bonded to the second wafer at a bonding interface between the first interconnect layer and the second interconnect layer.

6. The imaging sensor system of claim 5, wherein the first interconnect layer includes a first oxide, the second interconnect layer includes a second oxide, and wherein the bonding interface includes an interface between the first oxide and the second oxide.

7. The imaging sensor system of claim 5, wherein the first interconnect layer comprises at least N number of vias, wherein each of the N number of vias are coupled to a respective pixel of the SPAD imaging array to transfer the output pulses to the second interconnect layer at the bonding interface.

8. The imaging sensor system of claim 7, wherein the vias comprise micro through silicon vias (μ

TSV).

9. The imaging sensor system of claim 1, wherein each pixel comprises a quenching element coupled to a respective SPAD region to quench avalanching of the respective SPAD region by lowering a bias voltage.

10. An integrated circuit system, comprising:

a first wafer having a plurality of first dies, each first die including;

a single photon avalanche diode (SPAD) imaging array including a plurality of pixels formed in a first semiconductor layer, wherein the plurality of pixels include an N number of pixels, wherein substantially an entire thickness of the first semiconductor layer of each pixel is fully depleted such that a multiplication region included in each pixel near a front side of the first semiconductor layer is configured to be illuminated with photons through a back side of the first semiconductor layer and through the substantially entire thickness of the fully depleted first semiconductor layer;

deep n type isolation regions disposed in the first semiconductor layer between the pixels to isolate each one of the plurality of pixels from one another;

a first interconnect layer disposed on the front side of the first semiconductor layer; and

a second wafer having a plurality of second dies, each second die including;

a second interconnect layer disposed on the second semiconductor layer, wherein the first wafer is bonded to the second wafer at a bonding interface between the first interconnect layer and the second interconnect layer;

a plurality of digital counters formed in the second semiconductor layer and electrically coupled to the SPAD imaging array by way of the first and second interconnect layers, wherein the plurality of digital counters includes at least N number of digital counters, wherein each of the N number of digital counters are coupled to count output pulses generated by a respective SPAD region; and

control circuitry coupled to the SPAD imaging array to control operation of the SPAD imaging array.

11. The integrated circuit system of claim 10 wherein each second die further includes function logic coupled to the plurality of digital counters to store data read out from the SPAD imaging array.

12. The integrated circuit system of claim 10 wherein each of the plurality of digital counters formed in the second semiconductor layer comprises a separate complementary metal oxide semiconductor (CMOS) circuit disposed in the second semiconductor layer of the second wafer.

13. The integrated circuit system of claim 10 wherein each first die further includes a p+ doped region disposed on the back side of the first semiconductor layer.

14. The integrated circuit system of claim 10 wherein each of the N number of digital counters is coupled the respective one of the plurality of pixels through separate connections to respective terminals of the respective SPAD regions of the pixels.

15. The integrated circuit system of claim 10, wherein the first interconnect layer includes a first oxide, the second interconnect layer includes a second oxide, and wherein the bonding interface includes an interface between the first oxide and the second oxide.

16. The integrated circuit system of claim 10, wherein the first interconnect layer comprises at least N number of vias, wherein each of the N number of vias are coupled to a respective pixel of the SPAD imaging array to transfer the output pulses to the second interconnect layer at the bonding interface.

17. The integrated circuit system of claim 16 wherein the vias comprise micro through silicon vias (μ

TSV).

18. The integrated circuit system of claim 10, wherein each pixel comprises a quenching element coupled to a respective SPAD region to quench avalanching of the respective SPAD region by lowering a bias voltage.