Adaptive clocking scheme to accommodate supply voltage transients

• US 9,312,862 B2
• Filed: 12/20/2011
• Issued: 04/12/2016
• Est. Priority Date: 08/17/2011
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Penzes, Paul, Fullerton, Mark
• Primary Examiner(s): Choudhury, Zahid
• Application Number:
  US13/331,874
• Publication Number:
  US 20130047023A1
• Time in Patent Office: 1,575 Days
• Field of Search: 713/300, 713/310, 713/320, 713/322, 713/323, 713/400, 713/500
• US Class Current: 1/1
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C
• CPC Class Codes: G06F 1/32 Means for saving power
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3228 Monitoring task completion, e.g. by use of idle timers, stop commands or wait commands
• CPC Class Codes: G06F 12/14 Protection against unauthorised use of memory or access to memory
• CPC Class Codes: G06F 21/44 Program or device authentication
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H03K 19/01 Modifications for accelerating switching
• CPC Class Codes: H03K 2005/00019 Variable delay
• CPC Class Codes: H03K 2005/00026 controlled by an analog electrical signal, e.g. obtained after conversion by a D/A converter
• CPC Class Codes: H03K 2005/00058 controlled by a digital setting
• CPC Class Codes: H03K 3/0315 Ring oscillators
• CPC Class Codes: H03K 3/037 Bistable circuits
• CPC Class Codes: H03K 3/0375 provided with means for increasing reliability; for protection; for ensuring a predetermined initial state when the supply voltage has been applied; for storing the actual state when the supply voltage fails digital storage cells each combining volatile and non-volatile storage properties G11C14/00
• CPC Class Codes: H03K 5/133 using a chain of active delay devices
• CPC Class Codes: H03L 7/0802 the loop being adapted for reducing power consumption H03L7/14 takes precedence
• CPC Class Codes: H03L 7/097 using a comparator for comparing the voltages obtained from two frequency to voltage converters
• CPC Class Codes: H03L 7/0997 Controlling the number of delay elements connected in series in the ring oscillator

Abstract

Adaptive clocking schemes for synchronized on-chip functional blocks are provided. The clocking schemes enable synchronous clocking which can be adapted according to changes in signal path propagation delay due temperature, process, and voltage variations, for example. In embodiments, the clocking schemes allow for the capacity utilization of a logic path to be increased.

Claims

1. A system, comprising:

a first functional block;

a first latch circuit, coupled to an output of the first functional block;

a second functional block;

a second latch circuit, coupled to an input of the second functional block;

a logic path that couples a data output of the first latch circuit and a data input of the second latch circuit;

a clock path coupled at a first endpoint to a clock input of the first latch circuit and at a second endpoint to a clock input of the second latch circuit; and

a feedback path, coupled between a tap point of the clock path and the first endpoint of the clock path,

wherein the first latch circuit is configured to receive a system clock at its clock input and to sample the output of the first functional block according to the system clock, to send data clocked according to the system clock over the logic path,

wherein the second latch circuit is configured to receive the system clock at its clock input and to sample its data input according to the system clock, to receive the data from the logic path; and

wherein the clock path and the feedback path are configured to receive a same supply voltage as the logic path.

2. The system of claim 1, further comprising:

a clock module configured to generate the system clock and to provide the system clock to the first latch circuit.

3. The system of claim 2, wherein the clock module is configured to send the system clock over the clock path to the second latch circuit.

4. The system of claim 1, wherein the clock path and the feedback path form a ring oscillator circuit.

5. The system of claim 4, wherein an output frequency of the ring oscillator is a function of a propagation delay of the clock path.

6. The system of claim 5, wherein the output frequency of the ring oscillator is proportional to a propagation delay of a fraction of the clock path.

7. The system of claim 5, wherein the output frequency of the ring oscillator is configured to vary according to changes in supply voltage, thereby adjusting a frequency of the system clock based on supply voltage variations.

8. The system of claim 1, wherein a frequency of the system clock is configured to be a function of a propagation delay of the clock path.

9. The system of claim 8, wherein the propagation delay of the clock path is configured to be equal to a propagation delay of the logic path.

10. The system of claim 8, wherein the frequency of the system clock is configured to vary according to temperature, process, and voltage variations of the propagation delay of the clock path.

11. The system of claim 1, wherein the tap point is configured to be at least a minimum distance away from the first endpoint along the clock path so that the data sent over the logic path does not exceed a capacity of the logic path.

12. The system of claim 1, wherein the clock path is inside a phase-locked loop (PLL).

13. A method for regulating a clock frequency of an integrated circuit (IC), comprising:

estimating a supply voltage average over a time period by;

determining, based on an output of a ring oscillator, a number representative of an average speed of the ring oscillator over the time period; and

mapping the determined number to the supply voltage average;

determining an operating clock frequency for the IC based on the supply voltage average over the time period; and

adjusting the clock frequency of the IC to the determined operating clock frequency.

14. The method of claim 13, wherein determining the number representative of the average speed comprises coupling the output of the ring oscillator to a counter.

15. The method of claim 13, wherein mapping the determined number to the supply voltage average is performed using a lookup table, generated by a prior characterization of the ring oscillator.

16. The method of claim 13, wherein the ring oscillator is provided a same supply voltage as the IC.

17. The method of claim 13, wherein the determined operating clock frequency is the maximum frequency supported by the IC based on the supply voltage average.

18. A system for regulating a clock frequency of an integrated circuit (IC), comprising:

a ring oscillator configured to receive a same supply voltage as the IC;

a counter, coupled to an output of the ring oscillator, configured to determine a number representative of an average speed of the ring oscillator over a time period;

a first lookup table, coupled to the counter, configured to map the determined number to a supply voltage average;

a second lookup table configured to map the supply voltage average to an operating clock frequency for the IC; and

means for adjusting the clock frequency of the IC to the operating clock frequency.