Wave clocking

• US 9,312,863 B2
• Filed: 07/02/2014
• Issued: 04/12/2016
• Est. Priority Date: 08/17/2011
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Sippel, Tim
• Primary Examiner(s): Luu, An
• Application Number:
  US14/322,758
• Publication Number:
  US 20140312947A1
• Time in Patent Office: 650 Days
• Field of Search: 327/291, 327293-294, 327/298, 327155-159, 327/161
• US Class Current: 1/1
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C
• CPC Class Codes: G06F 1/32 Means for saving power
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3228 Monitoring task completion, e.g. by use of idle timers, stop commands or wait commands
• CPC Class Codes: G06F 12/14 Protection against unauthorised use of memory or access to memory
• CPC Class Codes: G06F 21/44 Program or device authentication
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H03K 19/01 Modifications for accelerating switching
• CPC Class Codes: H03K 2005/00019 Variable delay
• CPC Class Codes: H03K 2005/00026 controlled by an analog electrical signal, e.g. obtained after conversion by a D/A converter
• CPC Class Codes: H03K 2005/00058 controlled by a digital setting
• CPC Class Codes: H03K 3/0315 Ring oscillators
• CPC Class Codes: H03K 3/037 Bistable circuits
• CPC Class Codes: H03K 3/0375 provided with means for increasing reliability; for protection; for ensuring a predetermined initial state when the supply voltage has been applied; for storing the actual state when the supply voltage fails digital storage cells each combining volatile and non-volatile storage properties G11C14/00
• CPC Class Codes: H03K 5/133 using a chain of active delay devices
• CPC Class Codes: H03L 7/0802 the loop being adapted for reducing power consumption H03L7/14 takes precedence
• CPC Class Codes: H03L 7/097 using a comparator for comparing the voltages obtained from two frequency to voltage converters
• CPC Class Codes: H03L 7/0997 Controlling the number of delay elements connected in series in the ring oscillator

Abstract

Embodiments provide systems and methods for dynamically regulating the clock frequency of an integrated circuit (IC) based on the IC supply voltage. By doing so, the clock frequency is no longer constrained by a worst-case voltage level, and a higher effective clock frequency can be supported, increasing the IC performance. Embodiments include a wave clocking system which uses a plurality of delay chains configured to match substantially the delays of respective logic paths of the IC. As the delays of the logic paths vary with supply voltage and temperature changes, the delay chains matched to the logic paths experience substantially similar changes and are used to regulate the clock frequency of the IC.

Claims

1. A system for generating a clock signal in an integrated circuit (IC), comprising:

a wave clocking circuit configured to generate the clock signal;

a frequency monitor circuit configured to directly compare a frequency of the clock signal with a target frequency to generate a frequency error; and

a control circuit configured to generate a control signal based on the frequency error, the control signal being configured to adjust the frequency of the clock signal to reduce the frequency error,

wherein the wave clocking circuit comprises a delay chain with a delay matched to a predetermined delay, and

wherein the control signal is configured to adjust a supply voltage of the IC.

2. The system of claim 1, wherein the delay chain is configured to produce an output signal having a period that matches substantially the predetermined delay, and wherein the clock signal corresponds to the output signal of the delay chain.

3. The system of claim 2, wherein the control circuit is further configured to provide the control signal to the wave clocking circuit, and wherein the control signal is configured to adjust the delay chain to adjust the frequency of the clock signal.

4. The system of claim 1, wherein the delay chain includes a ring oscillator circuit.

5. The system of claim 1, wherein the delay chain includes a plurality of delay cells coupled in series.

6. The system of claim 1, wherein the target frequency is configured to be below a maximum logic supported frequency.

7. The system of claim 6, wherein the control circuit is further configured to limit the control signal to a value at or below a maximum value, the maximum value being configured to result in the frequency of the clock signal at a maximum allowable frequency below the maximum logic supported frequency.

8. The system of claim 1, further comprising:

a power manager,

wherein the control circuit is further configured to provide the control signal to the power manager, and

wherein the power manager is configured to adjust the supply voltage of the IC responsive to the control signal.

9. The system of claim 8, wherein the delay chain is responsive to the supply voltage of the IC.

10. The system of claim 8, wherein the adjusted supply voltage causes the frequency of the clock signal to decrease from a maximum allowable frequency to the target frequency.

11. The system of claim 1, wherein the frequency of the clock signal to reduce the frequency error is adjusted by the adjustment of the supply voltage of the IC.

12. A method for generating a clock signal for an integrated circuit (IC), comprising:

generating a signal having a period that matches substantially a predetermined delay;

designating the signal as the clock signal;

directly comparing a frequency of the clock signal with a target frequency to generate a frequency error;

generating a control signal based on the frequency error, the control signal being configured to adjust the frequency of the clock signal to reduce the frequency error; and

adjusting a supply voltage of the IC responsive to the control signal.

13. The method of claim 12, further comprising:

adjusting the period of the signal responsive to the control signal to adjust the frequency of the clock signal.

14. The method of claim 12, wherein the target frequency is configured to be at or below a maximum logic supported frequency.

15. The method of claim 12, wherein the period of the signal is responsive to the supply voltage of the IC.

16. The method of claim 12, wherein the adjusted supply voltage causes the frequency of the clock signal to decrease from a maximum allowable frequency to the target frequency.

17. The method of claim 12, wherein the frequency of the clock signal to reduce the frequency error is adjusted by the adjustment of the supply voltage of the IC.

18. A system for generating a clock signal for an integrated circuit (IC), comprising:

a wave clocking circuit configured to generate the clock signal;

a frequency monitor circuit configured to directly compare a frequency of the clock signal with a target frequency to generate a frequency error; and

a control circuit configured to generate a control signal based on the frequency error, the control signal being configured to adjust the frequency of the clock signal to reduce the frequency error,

wherein the control signal is further configured to adjust a supply voltage of the IC.

19. The system of claim 18, wherein the frequency of the clock signal to reduce the frequency error is adjusted by the adjustment of the supply voltage of the IC.

20. The system of claim 18, further comprising:

a delay chain, wherein the delay chain is configured to produce an output signal having a period that matches substantially the predetermined delay, and wherein the clock signal corresponds to the output signal of the delay chain.