AFLL with increased timing margin
First Claim
1. An integrated circuit, comprising a first sub-frequency-locked loop in an asymmetric frequency-locked loop (AFLL) that provides a clock signal, wherein the first sub-frequency-locked loop includes:
- a first digitally controlled oscillator (DCO) configured to output a first signal having a first fundamental frequency;
a second DCO configured to output a second signal having a second fundamental frequency;
a voltage regulator that provides a power-supply voltage to the second DCO; and
control logic, electrically coupled to the first DCO and the second DCO, configured to select one of the first DCO and the second DCO based on an instantaneous value of the power-supply voltage and an average power-supply voltage, wherein the AFLL is configured to modify a gain of the selected DCO in the first sub-frequency-locked loop based on the instantaneous value of the power-supply voltage and the average power-supply voltage, wherein the first DCO is associated with a time-critical path having a gate-dominated delay characteristic and the second DCO is associated with a time-critical path having a wire-dominated delay characteristic.
1 Assignment
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Accused Products
Abstract
In an integrated circuit that provides a clock signal, an asymmetric frequency-locked loop (AFLL) includes a first digitally controlled oscillator (DCO) that outputs a first signal having a first fundamental frequency, and a second DCO that outputs a second signal having a second fundamental frequency. The integrated circuit includes a voltage regulator that provides a power-supply voltage to the second DCO. Moreover, the AFLL includes control logic that selects one of the first DCO and the second DCO based on an instantaneous value of a power-supply voltage and an average power-supply voltage. Furthermore, the AFLL adjusts a gain of the selected DCO in the first sub-frequency-locked loop based on the instantaneous value of the power-supply voltage and the average power-supply voltage. In this way, an impact of power-supply voltage variations on a time-critical path in the integrated circuit is reduced.
4 Citations
18 Claims
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1. An integrated circuit, comprising a first sub-frequency-locked loop in an asymmetric frequency-locked loop (AFLL) that provides a clock signal, wherein the first sub-frequency-locked loop includes:
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a first digitally controlled oscillator (DCO) configured to output a first signal having a first fundamental frequency; a second DCO configured to output a second signal having a second fundamental frequency; a voltage regulator that provides a power-supply voltage to the second DCO; and control logic, electrically coupled to the first DCO and the second DCO, configured to select one of the first DCO and the second DCO based on an instantaneous value of the power-supply voltage and an average power-supply voltage, wherein the AFLL is configured to modify a gain of the selected DCO in the first sub-frequency-locked loop based on the instantaneous value of the power-supply voltage and the average power-supply voltage, wherein the first DCO is associated with a time-critical path having a gate-dominated delay characteristic and the second DCO is associated with a time-critical path having a wire-dominated delay characteristic. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. An electronic device, comprising:
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a processor; a memory storing a program module that is configured to be executed by the processor; and an integrated circuit, wherein the integrated circuit includes a first sub-frequency-locked loop in an asymmetric frequency-locked loop (AFLL) that provides a clock signal, wherein the first sub-frequency-locked loop includes; a first digitally controlled oscillator (DCO) configured to output a first signal having a first fundamental frequency; a second DCO configured to output a second signal having a second fundamental frequency; a voltage regulator that provides a power-supply voltage to the second DCO; and control logic, electrically coupled to the first DCO and the second DCO, configured to select one of the first DCO and the second DCO based on an instantaneous value of the power-supply voltage and an average power-supply voltage, wherein the AFLL is configured to modify a gain of the selected DCO in the first sub-frequency-locked loop based on the instantaneous value of the power-supply voltage and the average power-supply voltage, wherein the first DCO is associated with a time-critical path having a gate-dominated delay characteristic and the second DCO is associated with a time-critical path having a wire-dominated delay characteristic. - View Dependent Claims (11, 12, 13, 14, 15, 16)
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17. A method for operating an asymmetric frequency-locked loop (AFLL) that provides a clock signal, the method comprising:
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determining a power-supply voltage condition based on an instantaneous value of a power-supply voltage and an average power-supply voltage; selecting one of a first DCO and a second DCO in the AFLL based on the power-supply voltage condition, wherein the first DCO outputs a first signal having a first fundamental frequency and the second DCO outputs a second signal having a second fundamental frequency, wherein the first DCO is associated with a time-critical path having a gate-dominated delay characteristic and the second DCO is associated with a time-critical path having a wire-dominated delay characteristic; and adjusting a gain of the selected DCO in the AFLL based on the power-supply voltage condition. - View Dependent Claims (18)
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Specification