Electrical transceiver for synchronous Ethernet

• US 9,312,900 B2
• Filed: 10/17/2014
• Issued: 04/12/2016
• Est. Priority Date: 10/18/2013
• Status: Active Grant

• Current Assignee: Aimvalley B.V., OptoElectronics Solutions Co Ltd
• Original Assignee: Aimvalley B.V., OptoElectronics Solutions Co Ltd
• Inventors: Van Den Bosch, Willem, Schipper, Niels
• Primary Examiner(s): Garcia, Santiago
• Application Number:
  US14/516,995
• Publication Number:
  US 20150110162A1
• Time in Patent Office: 543 Days
• Field of Search: 375/219
• US Class Current: 1/1
• CPC Class Codes: H04B 1/38 Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
• CPC Class Codes: H04J 3/0667 Bidirectional timestamps, e.g. NTP or PTP for compensation of clock drift and for compensation of propagation delays arrangements for monitoring round trip delays in packet switching networks H04L43/0864
• CPC Class Codes: H04J 3/0673 using intermediate nodes, e.g. modification of a received timestamp before further transmission to the next packet node, e.g. including internal delay time or residence time into the packet
• CPC Class Codes: H04J 3/0697 Synchronisation in a packet node
• CPC Class Codes: H04L 12/40006 Architecture of a communication node current supply arrangements H04L12/10; intermediate storage or scheduling H04L49/90
• CPC Class Codes: H04L 7/0033 Correction by delay

Abstract

Disclosed is an electrical transceiver for synchronous Ethernet, including: a first interface connected with a host; a second interface including a physical layer (PHY) transceiver connected with a serial link; and a processor connected with the first interface and the second interface, wherein the processor includes a timing control unit controlling a transmission signal transmitted to the second interface from the first interface and a reception signal transmitted to the first interface from the second interface to have the same time delay.

Claims

1. An electrical transceiver for synchronous Ethernet comprising:

a first interface connected with a host;

a second interface including a physical layer (PHY) transceiver connected with a serial link; and

a processor connected with the first interface and the second interface,

wherein the processor includes a timing control unit controlling a transmission signal transmitted to the second interface from the first interface and a reception signal transmitted to the first interface from the second interface to have the same time delay, a decoding unit decoding a line coding signal received from the host and an encoding unit encoding the signal received from the serial link to the line coding signal,

wherein a delay difference between the transmission signal and the reception signal is calculated by Equation 1 below,

{fixed RX serdes+[n]×

8ns+fixed TX PHY}={fixed TX serdes+fixed EQ delay+fixed RX PHY} 

 

[Equation 1]

where, fixed RX serdes represents a delay time of the encoding unit, fixed TX PHY represents a delay time of a transmission unit in the physical layer (PHY) transceiver, fixed TX serdes represents a delay time of the decoding unit, fixed EQ delay represents a delay time in the timing control unit, and fixed RX PHY represents a delay time of a reception unit in the physical layer (PHY) transceiver, and [n] is a value at which the delays of the transmission signal and the reception signal are the same.

2. The electrical transceiver of claim 1, wherein the serial link is a 10/100/1000Base-T copper cable.

3. The electrical transceiver of claim 1, wherein:

the processor includes

a physical layer (PHY) interface connected with the physical layer (PHY) transceiver.

4. The electrical transceiver of claim 1, wherein the processor converts a 1.25 gigabit Ethernet serial packet signal to a 10/100/1000 Base-T line signal, and converts the 10/100/1000 Base-T line signal to the 1.25 gigabit Ethernet serial packet signal.

5. The electrical transceiver of claim 1, wherein

the timing control unit includes

a first buffer disposed between the decoding unit and the second interface, and

a second buffer disposed between the second interface and the encoding unit.

6. The electrical transceiver of claim 1, wherein:

the decoding unit decodes an 8b10b line coding signal to a 8-bit signal, and the encoding unit encodes the 8-bit signal to the 8b10b line coding signal.

7. The electrical transceiver of claim 1, further comprising:

a first PLL transmitting a transmission clock signal extracted from the signal transmitted from the host to the physical layer (PHY) transceiver; and

a second PLL transmitting a received clock signal extracted from the signal transmitted from the serial link to the encoding unit.