Compact and fast N-factorial single data rate clock and data recovery circuits

• US 9,313,058 B2
• Filed: 08/13/2014
• Issued: 04/12/2016
• Est. Priority Date: 03/07/2013
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Sengoku, Shoichiro, Wiley, George Alan, Lee, Chulkyu
• Primary Examiner(s): Dsouza, Adolf
• Application Number:
  US14/459,132
• Publication Number:
  US 20140348214A1
• Time in Patent Office: 608 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: H03L 7/00 Automatic control of frequency or phase; Synchronisation
• CPC Class Codes: H04L 25/14 Channel dividing arrangements , i.e. in which a single bit stream is divided between several baseband channels and reassembled at the receiver
• CPC Class Codes: H04L 25/40 Transmitting circuits; Receiving circuits repeater circuits, relay circuits H04L25/20
• CPC Class Codes: H04L 25/493 by transition coding, i.e. the time-position or direction of a transition being encoded before transmission
• CPC Class Codes: H04L 7/0276 Self-sustaining, e.g. by tuned delay line and a feedback path to a logical gate
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
• CPC Class Codes: H04L 7/04 Speed or phase control by synchronisation signals H04L7/0075 takes precedence

Abstract

A plurality of line interfaces is configured to receive a spread signal over the plurality of line interface. The spread signal carrying symbols with guaranteed symbol-to-symbol state transitions between consecutive symbols. The spread signal is defined by a plurality of transition signals including a first signal over a first line interface. A clock signal is extracted based on a comparison between a first instance of the first signal and a delayed second instance of the first signal. The delayed second instance of the first signal is sampled based on the clock signal to provide a symbol output. The clock extraction circuit is further adapted to generate the clock signal based on additional comparisons between a first instance of a second signal, within the plurality of transition signals, and a delayed second instance of the second signal, where the first and second signals are concurrent signals received over different line interfaces.

Claims

1. A receiver circuit, comprising:

a plurality of line interfaces configured to receive a spread signal distributed over the plurality of line interfaces, the spread signal carrying symbols with guaranteed symbol-to-symbol state transitions between consecutive symbols, the spread signal defined by a plurality of state transition signals including a first signal over a first line interface and a second signal over a second line interface;

a clock extraction circuit adapted to obtain a clock signal based on a comparison between a first instance of the first signal and a delayed second instance of the first signal, and a comparison between a first instance of the second signal and a delayed second instance of the second signal; and

a negative hold time logic circuit adapted to sample the delayed second instance of the first signal based on the clock signal and provide a symbol output.

2. The receiver circuit of claim 1, further comprising:

a plurality of differential receivers coupled to the plurality of line interfaces, wherein the first signal is a differential signal.

3. The receiver circuit of claim 1, further comprising:

a plurality of single-ended receivers coupled to the line interfaces, wherein the first signal is a single-ended signal.

4. The receiver circuit of claim 1, wherein the spread signal is one of a N-factorial (N!) encoded signal, a three-phase encoded signal, or a N-phase encoded signal having three or more phases.

5. The receiver circuit of claim 1, wherein the first signal and second signal are concurrent signals received over different line interfaces.

6. The receiver circuit of claim 1, wherein the negative hold time logic circuit includes a separate negative hold time logic device for each of the plurality of line interfaces, each separate negative hold time logic device adapted to concurrently sample a delayed instance of a distinct received signal, within the plurality of state transition signals, based on the clock signal and provide distinct symbol outputs.

7. The receiver circuit of claim 1, wherein the clock extraction circuit includes:

a comparator that compares the first instance of the first signal (SI) and the delayed instance of the first signal (SD) and outputs a comparison signal (NE);

a set-reset latch device that receives the comparison signal (NE) and outputs a filtered version of the comparison signal (NEFLT); and

a first analog delay device that delays the filtered version of the comparison signal (NEFLT) and outputs a delayed filtered version of the comparison signal (NEFLTD), where the delayed filtered version of the comparison signal (NEFLTD) serves to reset the set-reset latch device.

8. The receiver circuit of claim 7, wherein the negative hold time logic circuit includes a flip flop device that receives the delayed second instance of the first signal (SD) and outputs a symbol (S), where the flip flop device is triggered by the filtered version of the comparison signal (NEFLT).

9. The receiver circuit of claim 7, further comprising:

a second analog delay device that delays the first instance of the first signal and outputs the delayed second instance of the first signal.

10. The receiver circuit of claim 7, further comprising:

a latch device that captures the first instance of the first signal and outputs the delayed second instance of the first signal; and

a second analog delay device that delays the comparison signal (NE) and uses the delayed comparison signal (NED) to trigger the latch device.

11. The receiver circuit of claim 7, further comprising:

a latch device that captures the first instance of the first signal and outputs the delayed second instance of the first signal while either the filtered version of the comparison signal (NEFLT) or the delayed filtered version of the comparison signal (NEFLTD) is in a logical high state.

12. The receiver circuit of claim 11, further comprising:

an OR gate that receives as input the filtered version of the comparison signal (NEFLT) and the delayed filtered version of the comparison signal (NEFLTD) and outputs a signal used to trigger the latch device.

13. A method operational on a receiver circuit, comprising:

receiving a spread signal distributed over a plurality of line interfaces, the spread signal carrying symbols with guaranteed symbol-to-symbol state transitions between consecutive symbols, the spread signal defined by a plurality of state transition signals including a first signal over a first line interface and a second signal over a second line interface;

obtaining a clock signal based on a comparison between a first instance of the first signal and a delayed second instance of the first signal, and a comparison between a first instance of the second signal and a delayed second instance of the second signal; and

sampling the delayed second instance of the first signal based on the clock signal to provide a symbol output.

14. The method of claim 13, wherein the first signal is a single-ended signal.

15. The method of claim 13, wherein the spread signal is one of a N-factorial (N!) encoded signal, a three-phase encoded signal, or a N-phase encoded signal having three or more phases.

16. The method of claim 13, wherein the sampling of the delayed second instance of the first signal is done using a negative hold time logic circuit.

17. The method of claim 13, where the first signal and the second signal are concurrent signals received over different line interfaces.

18. The method of claim 13, further comprising:

concurrently sampling a delayed instance of a plurality of distinct signals, within the plurality of state transition signals, based on the clock signal and provide distinct symbol outputs.

19. The method of claim 13, wherein obtaining a clock signal includes:

comparing the first instance of the first signal (SI) and the delayed instance of the first signal (SD) to provide a comparison signal (NE);

latching the comparison signal (NE) to obtain a filtered version of the comparison signal (NEFLT); and

delaying the filtered version of the comparison signal (NEFLT) to provide a delayed filtered version of the comparison signal (NEFLTD), where the delayed filtered version of the comparison signal (NEFLTD) serves to latch the comparison signal (NE).

20. The method of claim 19, further comprising:

delaying the first instance of the first signal to obtain the delayed second instance of the first signal.

21. The method of claim 19, further comprising:

capturing the first instance of the first signal to obtain the delayed second instance of the first signal; and

delaying the comparison signal (NE) and using the delayed comparison signal (NED) to trigger the latching of the comparison signal (NE).

22. The method of claim 19, further comprising:

capturing the first instance of the first signal to obtain the delayed second instance of the first signal while either the filtered version of the comparison signal (NEFLT) or the delayed filtered version of the comparison signal (NEFLTD) is in a logical high state.

23. A receiver circuit, comprising:

means for receiving a spread signal distributed over a plurality of line interfaces, the spread signal carrying symbols with guaranteed symbol-to-symbol state transitions between consecutive symbols, the spread signal defined by a plurality of state transition signals including a first signal over a first line interface and a second signal over a second line interface;

means for obtaining a clock signal based on a comparison between a first instance of the first signal and a delayed second instance of the first signal, and a comparison between a first instance of the second signal and a delayed second instance of the second signal; and

means for sampling the delayed second instance of the first signal based on the clock signal to provide a symbol output.

24. The receiver circuit of claim 23, where the first signal and second signal are concurrent signals received over different line interfaces.

25. The receiver circuit of claim 23, further comprising:

means for concurrently sampling a delayed instance of a plurality of distinct signals, within the plurality of state transition signals, based on the clock signal and provide distinct symbol outputs.

26. The receiver circuit of claim 23, wherein obtaining a clock signal includes:

means for comparing the first instance of the first signal (SI) and the delayed instance of the first signal (SD) to provide a comparison signal (NE);

means for latching the comparison signal (NE) to obtain a filtered version of the comparison signal (NEFLT); and

means for delaying the filtered version of the comparison signal (NEFLT) to provide a delayed filtered version of the comparison signal (NEFLTD), where the delayed filtered version of the comparison signal (NEFLTD) serves to latch the comparison signal (NE).

27. The receiver circuit of claim 26, further comprising:

means for delaying the first instance of the first signal to obtain the delayed second instance of the first signal.

28. The receiver circuit of claim 26, further comprising:

means for capturing the first instance of the first signal to obtain the delayed second instance of the first signal; and

means for delaying the comparison signal (NE) and using the delayed comparison signal (NED) to trigger the latching of the comparison signal (NE).

29. The receiver circuit of claim 26, further comprising:

means for capturing the first instance of the first signal to obtain the delayed second instance of the first signal while either the filtered version of the comparison signal (NEFLT) or the delayed filtered version of the comparison signal (NEFLTD) is in a logical high state.