Expressing parallel execution relationships in a sequential programming language

• US 9,317,290 B2
• Filed: 01/07/2013
• Issued: 04/19/2016
• Est. Priority Date: 05/04/2007
• Status: Active Grant

• Current Assignee: NVIDIA Corporation
• Original Assignee: NVIDIA Corporation
• Inventors: Buck, Ian A., Aarts, Bastiaan
• Primary Examiner(s): Coleman, Eric
• Application Number:
  US13/735,438
• Publication Number:
  US 20130283015A1
• Time in Patent Office: 1,198 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 9/38 Concurrent instruction execution, e.g. pipeline or look ahead
• CPC Class Codes: G06F 9/522 Barrier synchronisation

Abstract

Circuits, methods, and apparatus that provide parallel execution relationships to be included in a function call or other appropriate portion of a command or instruction in a sequential programming language. One example provides a token-based method of expressing parallel execution relationships. Each process that can be executed in parallel is given a separate token. Later processes that depend on earlier processes wait to receive the appropriate token before being executed. In another example, counters are used in place to tokens to determine when a process is completed. Each function is a number of individual functions or threads, where each thread performs the same operation on a different piece of data. A counter is used to track the number of threads that have been executed. When each thread in the function has been executed, a later function that relies on data generated by the earlier function may be executed.

Claims

1. A method of processing data comprising:

receiving a first command instructing a first process to be executed on a processing circuit, the first command including a first indication that may be used to indicate when the first process has completed execution;

receiving a second command instructing a second process to be executed on the processing circuit, the second command including a second indication that may be used to indicate when the second process has completed execution;

receiving a third command instructing a third process to be executed on the processing circuit, the third command instructing the third process not to begin until the first indication and the second indication have been received, wherein data generated by the third process is stored in a memory, and

wherein the first command, the second command, and the third command are compatible with a sequential programming language.

2. The method of claim 1 wherein the first indication is a token.

3. The method of claim 1 wherein the first indication is a count provided by a counter.

4. The method of claim 1 wherein the first command is compatible with a C++ programming language.

5. The method of claim 1 wherein the processing circuit comprises a single-instruction multiple-data processor.

6. The method of claim 1 wherein the processing circuit comprises a plurality of single-instruction multiple-data processors.

7. The method of claim 1 further comprising:

receiving one or more commands to use the stored data to generate display data and to display the display data.

8. An integrated circuit comprising:

a processing circuit capable of executing at least a first and a second process;

a first counter configured to track a number of times the first process has been executed on the processing circuit;

a second counter configured to track a number of times the second process has been executed on the processing circuit; and

a memory interface circuit to receive a plurality of instructions from a command buffer in a memory,

wherein one of the plurality of instructions prevent execution of a third process until the first counter reaches a first number and the second counter reaches a second number, and

wherein the plurality of instructions are compatible with a sequential programming language.

9. The integrated circuit of claim 8 wherein the plurality of instructions are compatible with a C++ programming language.

10. The integrated circuit of claim 8 wherein the processing circuit comprises a single-instruction multiple-data processor.

11. The integrated circuit of claim 8 wherein the processing circuit comprises a plurality of single-instruction multiple-data processors.

12. The integrated circuit of claim 11 wherein the integrated circuit is a graphics processing integrated circuit.

13. A method of processing data comprising:

receiving a first command to execute a first process a first number of times on a processing circuit;

receiving a second command to execute a second process a second number of times on the processing circuit;

tracking a number of times the first process has been executed on the processing circuit;

tracking a number of times the second process has been executed on the processing circuit;

determining that the first process has been executed the first number of times on the processing circuit;

determining that the second process has been executed the second number of times on the processing circuit;

receiving a third command to execute, after the first process has been executed the first number of times and the second process has been executed the second number of times, a third process a third number of times on the processing circuit; and

then

receiving one or more additional commands to use data generated by the third process to generate display data and to display the display data,

wherein the first, second, and third commands are compatible with a sequential programming language.

14. The method of claim 13 wherein the sequential programming language is a C based programming language.

15. The method of claim 13 wherein the sequential programming language is a C++ programming language.

16. The method of claim 13 wherein the processing circuit comprises a plurality of single-instruction multiple-data processors.