Characterization of within-die variations of many-core processors
First Claim
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1. A method for operating a many-core processor including resilient cores, comprising:
- determining a frequency variation map for the many-core processor if there is an upgrade to a software application; and
scheduling execution of a plurality of tasks on respective resilient cores from the resilient cores of the many-core processor in accordance to the frequency variation map,wherein the determining of the frequency variation map includes;
dynamically increasing a clock frequency at which the resilient cores execute instructions;
executing the instructions on the resilient cores;
monitoring to determine at which clock frequency an error occurs at each resilient core from the resilient cores; and
constructing the frequency variation map based on a maximum tolerable frequency/voltage ratio for each resilient core from the resilient cores.
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Abstract
A system and method for operating a many-core processor including resilient cores may include determining a frequency variation map for the many-core processor and scheduling execution of a plurality of tasks on respective resilient cores of the many-core processor in accordance to the frequency variation map.
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Citations
20 Claims
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1. A method for operating a many-core processor including resilient cores, comprising:
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determining a frequency variation map for the many-core processor if there is an upgrade to a software application; and scheduling execution of a plurality of tasks on respective resilient cores from the resilient cores of the many-core processor in accordance to the frequency variation map, wherein the determining of the frequency variation map includes; dynamically increasing a clock frequency at which the resilient cores execute instructions; executing the instructions on the resilient cores; monitoring to determine at which clock frequency an error occurs at each resilient core from the resilient cores; and constructing the frequency variation map based on a maximum tolerable frequency/voltage ratio for each resilient core from the resilient cores. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A many-core processor, comprising:
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resilient cores; and a storage for storing a frequency variation map if there is an upgrade to a software application, wherein a plurality of tasks is scheduled to execute on respective resilient cores from the resilient cores of the many-core processor in accordance to the frequency variation map, and wherein the frequency variation map is determined by; dynamically increasing a clock frequency at which the resilient cores execute instructions; executing the instructions on the resilient cores; monitoring to determine at which clock frequency an error occurs at each resilient core from the resilient cores; and constructing the frequency variation map based on a maximum tolerable frequency/voltage ratio for each resilient core from the resilient cores. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16)
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17. A system comprising:
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a many-core processor including resilient cores; and a memory accessible by each resilient core from of the resilient cores for storing a frequency variation map if there is an upgrade to a software application, wherein a plurality of tasks is scheduled to execute on respective resilient cores from the resilient cores of the many-core processor in accordance to the frequency variation map, and wherein the frequency variation map is determined by; dynamically increasing a clock frequency at which the resilient cores execute instructions; executing the instructions on the resilient cores; monitoring to determine at which clock frequency an error occurs at each resilient core from the resilient cores; and constructing the frequency variation map based on a maximum tolerable frequency/voltage ratio for each resilient core from the resilient cores. - View Dependent Claims (18, 19, 20)
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Specification