Characterization of within-die variations of many-core processors

• US 9,317,342 B2
• Filed: 12/23/2011
• Issued: 04/19/2016
• Est. Priority Date: 12/23/2011
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Dighe, Saurabh
• Primary Examiner(s): Puente, Emerson
• Assistant Examiner(s): Sun, Charlie
• Application Number:
  US13/995,048
• Publication Number:
  US 20130318539A1
• Time in Patent Office: 1,579 Days
• Field of Search: 718/105
• US Class Current: 1/1
• CPC Class Codes: G06F 1/329 by task scheduling
• CPC Class Codes: G06F 9/4893 taking into account power or heat criteria power management in computers in general G06F1/3203; thermal management in computers in general G06F1/206
• CPC Class Codes: G06F 9/54 Interprogram communication
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A system and method for operating a many-core processor including resilient cores may include determining a frequency variation map for the many-core processor and scheduling execution of a plurality of tasks on respective resilient cores of the many-core processor in accordance to the frequency variation map.

Claims

1. A method for operating a many-core processor including resilient cores, comprising:

determining a frequency variation map for the many-core processor if there is an upgrade to a software application; and

scheduling execution of a plurality of tasks on respective resilient cores from the resilient cores of the many-core processor in accordance to the frequency variation map,

wherein the determining of the frequency variation map includes;

dynamically increasing a clock frequency at which the resilient cores execute instructions;

executing the instructions on the resilient cores;

monitoring to determine at which clock frequency an error occurs at each resilient core from the resilient cores; and

constructing the frequency variation map based on a maximum tolerable frequency/voltage ratio for each resilient core from the resilient cores.

2. The method of claim 1, further comprising:

creating a schedule in accordance to the frequency variation map; and

executing the plurality of tasks on the many-core processor in accordance to the schedule.

3. The method of claim 1, wherein at least one resilient core from the resilient cores includes an instruction pipeline, an error control unit, and an adaptive clock control.

4. The method of claim 3, wherein the instruction pipeline further includes pipeline stages, wherein at least one of the pipeline stages is guardband-protected.

5. The method of claim 3, wherein the error control unit generates a replay signal if the error control unit detects an occurrence of an error during executing an instruction on the instruction pipeline.

6. The method of claim 3, wherein the adaptive clock control, based on a number of repeated erroneous executions of an instruction, generates a clock adjusting signal to slow down a clock frequency generated by a clock generator.

7. The method of claim 1, further comprising determining the frequency variation map for the many-core processor every six months.

8. The method of claim 1, further comprising determining the frequency variation map for the many-core processor based on humidity.

9. A many-core processor, comprising:

resilient cores; and

a storage for storing a frequency variation map if there is an upgrade to a software application,

wherein a plurality of tasks is scheduled to execute on respective resilient cores from the resilient cores of the many-core processor in accordance to the frequency variation map, and

wherein the frequency variation map is determined by;

dynamically increasing a clock frequency at which the resilient cores execute instructions;

executing the instructions on the resilient cores;

monitoring to determine at which clock frequency an error occurs at each resilient core from the resilient cores; and

constructing the frequency variation map based on a maximum tolerable frequency/voltage ratio for each resilient core from the resilient cores.

10. The processor of claim 9, wherein the plurality of tasks are executed on the many-core processor in accordance to a schedule that was created in accordance to the frequency variation map.

11. The processor of claim 9, wherein at least one resilient core from the resilient cores includes an instruction pipeline, an error control unit, and an adaptive clock control.

12. The processor of claim 11, wherein the instruction pipeline further includes pipeline stages, wherein at least one of the pipeline stages is guardband-protected.

13. The processor of claim 11, wherein the error control unit generates a replay signal if the error control unit detects an occurrence of an error during executing an instruction on the instruction pipeline.

14. The processor of claim 11, wherein the adaptive clock control, based on a number of repeated erroneous executions of an instruction, generates a clock adjusting signal to slow down a clock frequency generated by a clock generator.

15. The processor of claim 9, wherein the frequency variation map for the many-core processor is determined every six months.

16. The processor of claim 9, wherein the frequency variation map for the many-core processor is determined based on humidity.

17. A system comprising:

a many-core processor including resilient cores; and

a memory accessible by each resilient core from of the resilient cores for storing a frequency variation map if there is an upgrade to a software application,

wherein a plurality of tasks is scheduled to execute on respective resilient cores from the resilient cores of the many-core processor in accordance to the frequency variation map, and

wherein the frequency variation map is determined by;

dynamically increasing a clock frequency at which the resilient cores execute instructions;

executing the instructions on the resilient cores;

monitoring to determine at which clock frequency an error occurs at each resilient core from the resilient cores; and

constructing the frequency variation map based on a maximum tolerable frequency/voltage ratio for each resilient core from the resilient cores.

18. The system of claim 17, wherein the plurality of tasks are executed on the many-core processor in accordance to a schedule that was created in accordance to the frequency variation map.

19. The system of claim 17, wherein at least one resilient core from the resilient cores includes an instruction pipeline, an error control unit, and an adaptive clock control.

20. The system of claim 17, wherein the frequency variation map for the many-core processor is determined one of (1) every six months, and (2) based on humidity.