Apparatus and method for implementing a multi-level memory hierarchy over common memory channels
First Claim
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1. A computer system comprising:
- a) a processor comprising a plurality of cores to execute instructions and process data and one or more processor caches to cache instructions and data according to a first cache management policy;
b) a first memory channel comprising a first set of address and data lines coupled to the processor;
c) a second memory channel comprising a second set of address and data lines coupled to the processor;
d) a first first-level memory and a second first-level memory each comprising a first set of characteristics associated therewith, the first set of characteristics including a first read access speed and a first write access speed, the first first-level memory coupled to the first memory channel and the second first-level memory coupled to the second memory channel; and
e) a first second-level memory communicatively coupled to the first memory channel, and a second second-level memory communicatively coupled to the second memory channel, the first and second second-level memories including a second set of characteristics associated therewith, the second set of characteristics including;
i) second read and write access speeds wherein at least one of the second read and write access speeds is relatively lower than either the first read access speed or first write access speed, respectively,ii) non-volatility such that the first and second second-level memories are to maintain content if power to the first and second-level memories is removed, wherein at least a portion of the first first-level memory is configured as a first cache for instructions and/or data stored in the first second-level memory and at least a portion of the second first-level memory is configured as a second cache for instructions and/or data stored in the second second-level memory;
f) first-level memory controller circuitry to implement said at least a portion of the first first-level memory and said at least a portion of the second first-level memory as the first and second caches;
g) second-level memory interface circuitry to generate memory channel addresses to access the first second-level memory and the second second-level memory.
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Abstract
A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as “far memory.” Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as “near memory.”
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Citations
39 Claims
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1. A computer system comprising:
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a) a processor comprising a plurality of cores to execute instructions and process data and one or more processor caches to cache instructions and data according to a first cache management policy; b) a first memory channel comprising a first set of address and data lines coupled to the processor; c) a second memory channel comprising a second set of address and data lines coupled to the processor; d) a first first-level memory and a second first-level memory each comprising a first set of characteristics associated therewith, the first set of characteristics including a first read access speed and a first write access speed, the first first-level memory coupled to the first memory channel and the second first-level memory coupled to the second memory channel; and e) a first second-level memory communicatively coupled to the first memory channel, and a second second-level memory communicatively coupled to the second memory channel, the first and second second-level memories including a second set of characteristics associated therewith, the second set of characteristics including; i) second read and write access speeds wherein at least one of the second read and write access speeds is relatively lower than either the first read access speed or first write access speed, respectively, ii) non-volatility such that the first and second second-level memories are to maintain content if power to the first and second-level memories is removed, wherein at least a portion of the first first-level memory is configured as a first cache for instructions and/or data stored in the first second-level memory and at least a portion of the second first-level memory is configured as a second cache for instructions and/or data stored in the second second-level memory; f) first-level memory controller circuitry to implement said at least a portion of the first first-level memory and said at least a portion of the second first-level memory as the first and second caches; g) second-level memory interface circuitry to generate memory channel addresses to access the first second-level memory and the second second-level memory. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
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17. A computer system comprising:
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a) a processor comprising a plurality of cores to execute instructions and process data and one or more processor caches to cache instructions and data according to a first cache management policy; b) a first memory channel comprising a set of address and data lines coupled to the processor; c) a first level memory comprising a first set of characteristics associated therewith, the first set of characteristics including a first read access speed and a first write access speed, the first level memory communicatively coupled to the first memory channel; and d) a second level memory communicatively coupled to the first memory channel, the second level memory comprising a second set of characteristics associated therewith, the second set of characteristics including; i) second read and write access speeds wherein at least one of the second read and write access speeds is relatively lower than either the first read access speed or first write access speed, respectively, ii) non-volatility such that the second level memory is to maintain its content if power to the second level memory is removed, iii) random access and byte addressability such that instructions and/or data stored therein may be randomly accessed at a granularity equivalent to that used by a memory subsystem of the system; e) first-level memory controller circuitry to implement at least a portion of the first first-level memory as a cache for the second level memory; f) second-level memory interface circuitry to communicate with second-level memory controller circuitry. - View Dependent Claims (18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30)
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31. An apparatus comprising:
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a memory controller comprising; a) a first memory channel interface to couple to a first first-level memory and a first second-level memory; b) a second memory channel interface to couple to a second first-level memory and a second second-level memory, wherein, the first and second first-level memories comprise a first set of characteristics associated therewith, the first set of characteristics including a first read access speed and a first write access speed, and wherein the first and second second-level memories comprise a second set of characteristics associated therewith, the second set of characteristics including; i) second read and write access speeds wherein at least one of the second read and write access speeds is relatively lower than either the first read access speed or first write access speed, respectively, ii) non-volatility such that the second-level memories are to maintain their content if power is removed from the second-level memories, iii) random access and byte addressability such that instructions or data stored therein may be randomly accessed at a granularity equivalent to that used by a memory subsystem of the system, c) a first controller coupled to the first and second memory channel interfaces, the first controller to communicate to the first first-level memory through the first memory channel interface and to communicate to the second first-level memory through the second memory channel interface; and
,d) second-level memory interface circuitry to communicate to a first second-level memory controller through the first memory channel interface and communicate to a second second-level memory controller through the second memory channel interface. - View Dependent Claims (32, 33, 34, 35, 36, 37, 38, 39)
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Specification