Distributed hardware device simulation

• US 9,317,637 B2
• Filed: 01/14/2011
• Issued: 04/19/2016
• Est. Priority Date: 01/14/2011
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Archer, Charles J., Blocksome, Michael A., Ratterman, Joseph D., Smith, Brian E.
• Primary Examiner(s): Silver, David
• Application Number:
  US13/006,696
• Publication Number:
  US 20120185230A1
• Time in Patent Office: 1,922 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 2111/02 CAD in a network environment, e.g. collaborative CAD or distributed simulation
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking
• CPC Class Codes: G06F 9/5077 Logical partitioning of resources; Management or configuration of virtualized resources specific details on emulation or internal functioning of virtual machines G06F9/455

Abstract

Distributed hardware device simulation, including: identifying a plurality of hardware components of the hardware device; providing software components simulating the functionality of each hardware component, wherein the software components are installed on compute nodes of a distributed processing system; receiving, in at least one of the software components, one or more messages representing an input to the hardware component; simulating the operation of the hardware component with the software component, thereby generating an output of the software component representing the output of the hardware component; and sending, from the software component to at least one other software component, one or more messages representing the output of the hardware component.

Claims

1. An apparatus for distributed hardware device simulation, the apparatus comprising a computer processor, a computer memory operatively coupled to the computer processor, the computer memory having disposed within it computer program instructions that, when executed by the computer processor, cause the apparatus to carry out the steps of:

identifying a plurality of hardware components of the distributed hardware device;

providing software components simulating the functionality of each hardware component, wherein each software component is installed on a distinct compute node of a plurality of compute nodes of a distributed processing system, wherein;

the plurality of compute nodes are configured in a tree network topology and each compute node is assigned a unique rank, each rank uniquely identifying a compute node'"'"'s location in the tree network topology for point-point data communications and for collective operations;

each compute node comprises one or more computer processing cores, a computer memory, and input/output adapters, and

the compute nodes are coupled for data communications by a plurality of independent data communications networks;

receiving, in a first software component installed on a first compute node, one or more messages representing an input to the hardware component corresponding to the first software component;

simulating the operation of the hardware component by the first software component, thereby generating an output of the first software component representing the output of the hardware component;

sending, from the first software component installed on the first compute node to at least a second software component installed on a second compute node, one or more messages representing the output of the hardware component corresponding to the first software component, wherein the one or more messages are transmitted via at least one of the plurality of independent data communications networks;

simulating the operation of the hardware component by the second software component using the output of the first software component representing the output of the hardware component as an input, thereby generating an output of the second software component representing the output of the hardware component; and

determining, from the one or more messages of the first software components, whether the corresponding hardware device as designed is valid, including verifying that the output messages do not include error messages and verifying that the output messages include output values that are within acceptable ranges.

2. The apparatus of claim 1 further comprising computer program instructions that, when executed by the computer processor, cause the apparatus to carry out the steps of:

modifying the first software component to represent a modified version of the corresponding hardware component of the hardware device;

simulating the operation of the modified version of the corresponding hardware component with the modified software component, thereby generating a new output of the first software component representing the output of a modified version of the hardware component; and

sending, from the modified software component to at least one other software component, one or more messages representing the new output of the modified version of the hardware component.

3. The apparatus of claim 1 further comprising computer program instructions that, when executed by the computer processor, cause the apparatus to carry out the steps of:

modifying the second software component representing a second hardware component of the hardware device;

requesting, from the second software component, simulation of the hardware component corresponding to the first software component, thereby generating new inputs for the modified second software component;

simulating, by the second software component, the operation of the second hardware component using the new inputs, thereby generating a new output of the modified second software component representing the output of a modified version of the second hardware component; and

sending, from the modified software component to at least a third software component, one or more messages representing the new output of the second hardware component.

4. A computer program product for distributed hardware device simulation, the computer program product disposed upon a computer readable storage medium, wherein the computer readable storage medium is not a signal, the computer program product comprising computer program instructions that, when executed, cause a computer to carry out the steps of:

identifying a plurality of hardware components of the distributed hardware device;

providing software components simulating the functionality of each hardware component, wherein each software component is installed on a distinct compute node of a plurality of compute nodes of a distributed processing system, wherein;

the plurality of compute nodes are configured in a tree network topology and each compute node is assigned a unique rank, each rank uniquely identifying a compute node'"'"'s location in the tree network topology for point-point data communications and for collective operations;

each compute node comprises one or more computer processing cores, a computer memory, and input/output adapters, and

the compute nodes are coupled for data communications by a plurality of independent data communications networks;

receiving, in a first software component installed on a first compute node, one or more messages representing an input to the hardware component corresponding to the first software component;

simulating the operation of the hardware component by the first software component, thereby generating an output of the first software component representing the output of the hardware component;

sending, from the first software component installed on the first compute node to at least a second software component installed on a second compute node, one or more messages representing the output of the hardware component corresponding to the first software component, wherein the one or more messages are transmitted via at least one of the plurality of independent data communications networks;

simulating the operation of the hardware component by the second software component using the output of the first software component representing the output of the hardware component as an input, thereby generating an output of the second software component representing the output of the hardware component; and

determining, from the one or more messages of the first software components, whether the corresponding hardware device as designed is valid, including verifying that the output messages do not include error messages and verifying that the output messages include output values that are within acceptable ranges.

5. The computer program product of claim 4 further comprising computer program instructions that, when executed, cause a computer to carry out the steps of:

modifying the first software component to represent a modified version of the corresponding hardware component of the hardware device;

simulating the operation of the corresponding hardware component with the modified software component, thereby generating a new output of the first software component representing the output of a modified version of the hardware component; and

sending, from the modified software component to at least one other software component, one or more messages representing the new output of the modified version of the hardware component.

6. The computer program product of claim 4 further comprising computer program instructions that, when executed, cause a computer to carry out the steps of:

modifying the second software component representing a second hardware component of the hardware device;

requesting, from the second software component, simulation of the hardware component corresponding to the first software component, thereby generating new inputs for the modified second software component;

simulating, by the second software component, the operation of the second hardware component using the new inputs, thereby generating a new output of the modified second software component representing the output of a modified version of the second hardware component; and

sending, from the modified software component to at least a third software component, one or more messages representing the new output of the second hardware component.