Partial page memory operations

• US 9,318,199 B2
• Filed: 10/26/2012
• Issued: 04/19/2016
• Est. Priority Date: 10/26/2012
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Abraham, Michael, Tanaka, Tomoharu, Kawai, Koichi, Einaga, Yuichi
• Primary Examiner(s): CARDWELL, ERIC
• Application Number:
  US13/661,321
• Publication Number:
  US 20140122773A1
• Time in Patent Office: 1,271 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/107 Programming all cells in an array, sector or block to the same state prior to flash erasing
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits

Abstract

Apparatuses may include a memory block with strings of memory cells formed in a plurality of tiers. The apparatus may further comprise access lines and data lines shared by the strings, with the access lines coupled to the memory cells corresponding to a respective tier of the plurality of tiers. The memory cells corresponding to at least a portion of the respective tier may comprise a respective page of a plurality of pages. Subsets of the data lines may be mapped into a respective partial page of a plurality of partial pages of the respective page. Each partial page may be independently selectable from other partial pages. Additional apparatuses and methods are disclosed.

Claims

1. An apparatus comprising a memory block, the memory block comprising:

strings of memory cells formed in a plurality of tiers;

access lines shared by the strings, each access line coupled to the memory cells corresponding to a respective tier of the plurality of tiers, the memory cells corresponding to at least a portion of the respective tier comprising a respective page of a plurality of pages; and

data lines shared by the strings, the data lines comprising a plurality of subsets of data lines, each subset of data lines being mapped into a respective partial page of a plurality of partial pages of the respective page, each partial page independently selectable from other partial pages within the respective page, wherein a particular page of the plurality of pages includes a first partial page and a second partial page, memory cells corresponding to the first partial page are coupled to a particular access line of the access line via a first string driver, and memory cells corresponding to the second partial page are coupled to the particular access line via a second string driver.

2. The apparatus of claim 1, wherein each of the plurality of partial pages comprises a tile.

3. The apparatus of claim 1, wherein each of the plurality of partial pages comprises a tile group, each tile group including a plurality of tiles.

4. The apparatus of claim 1, wherein each of the plurality of partial pages comprises a tile group gather, each tile group gather including a plurality of tile groups.

5. The apparatus of claim 4, wherein the plurality of tile groups included in the tile group gather are proximately related according to a numerical address sequence.

6. The apparatus of claim 4, wherein at least one of the plurality of tile groups included in the tile group gather is proximately unrelated according to a numerical address sequence.

7. The apparatus of claim 1, further comprising:

a control unit to map write data into the respective page of the respective tier such that a first portion of the write data will be programmed into a first partial page of the partial pages, and a second portion of the write data will be programmed into a second partial page of the partial pages, upon receiving a command to write the write data at the control unit.

8. The apparatus of claim 7, wherein the control unit is configured to:

trigger programming the write data in the respective page of the respective tier prior to a page buffer associated with the block being filled.

9. The apparatus of claim 7, wherein the control unit is configured to:

program the first portion into the first partial page; and

program the second portion into the second partial page after programming the first portion into the first partial page and without first erasing the memory block.

10. An apparatus comprising a memory block, the memory block comprising:

strings of memory cells formed in a plurality of tiers;

access lines shared by the strings, each access line coupled to the memory cells corresponding to a respective tier of the plurality of tiers, the memory cells corresponding to at least a portion of the respective tier comprising a respective page of a plurality of pages; and

data lines shared by the strings, the data lines comprising a plurality of subsets of data lines, each subset of data lines being mapped into a respective partial page of a plurality of partial pages of the respective page including a first partial page and a second partial page, each partial page independently selectable from other partial pages such that a single memory operation can be independently performed on the first partial page and the second partial page within the respective page, wherein memory cells corresponding to the first partial page of a particular page of the plurality of pages are coupled to a particular access line of the access line via a first string driver, and memory cells corresponding to the second partial page of the particular page are coupled to the particular access line via a second string driver.

11. The apparatus of claim 10, further comprising:

a control unit to select at least one of the first partial page or the second partial page based on column addresses associated with data for the single memory operation.

12. A method comprising:

receiving data from a host;

mapping the data into a page selected from a plurality of pages, each of the plurality of pages corresponding to one of a plurality of tiers in a memory block, the page comprising a plurality of partial pages including a first partial page and a second partial page, each partial page independently selectable from other partial pages, the mapping including mapping a first portion of the data into the first partial page, and a second portion of the data into the second partial page, wherein memory cells corresponding to the first partial page of a particular page of the plurality of pages are coupled to an access line via a first string driver, and memory cells corresponding to the second partial page of the particular page are coupled to the access line via a second string driver;

programming the first portion of the data into the first partial page; and

programming the second portion of the data into the second partial page independently of the first portion of the data programmed in the first partial page.

13. The method of claim 12, wherein the receiving comprises:

initiating a page program including programming of the first partial page before a page buffer receiving the data is filled.

14. The method of claim 12, wherein the mapping of the data comprises:

splitting the data into the portions based at least in part on a size of the page and a number of the partial pages.

15. The method of claim 12, wherein the mapping of the data comprises:

selecting, as the first and second partial pages, two of the plurality of partial pages proximately related according to a numerical address sequence.

16. The method of claim 12, wherein the mapping of the data comprises:

selecting, as the first and second partial pages, two of the plurality of partial pages proximately unrelated according to a numerical address sequence.

17. The method of claim 12, wherein the programming of the first portion comprises:

activating a first set of data lines corresponding to the first partial page; and

disabling other data lines including a second set of data lines corresponding to the second partial page.

18. The method of claim 17, wherein the programming of the second portion comprises:

activating the second set of data lines; and

disabling other data lines including the first set of data lines.

19. The method of claim 12, wherein the programming of the second portion of the data comprises programming the second portion of the data without first erasing the selected page after programming the first portion of the data.

20. The method of claim 12, wherein the programming of the second portion comprises:

refraining from programming the first partial page.

21. The method of claim 12, further comprising:

mapping column addresses within the page into the plurality of partial pages corresponding to the page, prior to receiving the data.

22. The method of claim 21, further comprising:

reporting a mapping relationship between the column addresses and the plurality of partial pages to the host.

23. A method of operating a memory block, the memory block comprising a plurality of pages, each page of the plurality of pages corresponding to one of a plurality of tiers and each page comprising a plurality of partial pages, the method comprising:

receiving a request for a memory operation;

selecting a page from the plurality of pages as a target page;

selecting a first partial page of the target page to perform the memory operation; and

selecting a second partial page of the target page to perform the memory operation independently of the first partial page, wherein memory cells corresponding to the first partial page of a particular page of the plurality of pages are coupled to an access line via a first string driver, and memory cells corresponding to the second partial page of the particular page are coupled to the access line via a second string driver.

24. The method of claim 23, wherein the memory operation comprises a program operation, a read operation, a verify operation, or an erase operation.

25. A method comprising:

receiving, at a memory device, a first partial page of data from a host;

programming the first partial page of data into a first group of memory cells of a selected page;

receiving, at the memory device, a second partial page of data after the first partial page of data is programmed into the first group of memory cells of the selected page;

programming the second partial page of data into a second group of memory cells of the selected page without first erasing the particular page or reprogramming the first partial page of data programmed into the first group of memory cells of the selected page; and

refraining from tracking, in the memory device, which partial pages of the selected page have already been programmed.

26. The method of claim 25, wherein the first and second partial pages of data are to be received at a same data rate.

27. The method of claim 25, further comprising:

tracking, in the host, which partial pages of the selected page have already been programmed.

28. A method comprising:

receiving, at a memory device, a first partial page of data from a host;

programming the first partial page of data into a first group of memory cells of a selected page;

receiving, at the memory device, a second partial page of data after the first partial page of data is programmed into the first group of memory cells of the selected page;

programming the second partial page of data into a second group of memory cells of the selected page without first erasing the particular page or reprogramming the first partial page of data programmed into the first group of memory cells of the selected page;

refraining from tracking, in the memory device, which partial pages of the selected page have already been programmed; and

refraining from programming partial pages of the selected page into which no data to be written is mapped.

29. The method of claim 28, further comprising:

reporting to the host a partial page programming size.

30. The method of claim 28, further comprising:

adjusting a programming algorithm as ramp rates change.

31. The method of claim 28, further comprising:

when reading a lower page of the selected page with only a portion of the lower page being programmed, returning read data only for partial pages that have been programmed.

32. The method of claim 28, further comprising:

when reading a lower page of the selected page with only a portion of an upper page being programmed, adjusting a read algorithm for reading memory cells of the selected page that do not have their upper page programmed.

33. The method of claim 28, further comprising:

when reading an upper page of the selected page, returning read data only for partial pages that have had their upper page programmed.

34. The method of claim 28, further comprising:

reading all memory cells of the selected page; and

returning data to the host only for valid, programmed partial pages.