Digitally controlled source side select gate offset in 3D NAND memory erase

• US 9,318,209 B1
• Filed: 03/24/2015
• Issued: 04/19/2016
• Est. Priority Date: 03/24/2015
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Inventors: Huynh, Jonathan, Park, Jongmin, Chen, Maurice, Kuo, Tien chien
• Primary Examiner(s): Nguyen, Tuan T
• Application Number:
  US14/667,014
• Time in Patent Office: 392 Days
• US Class Current: 1/1
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/24 Bit-line control circuits
• CPC Class Codes: G11C 16/32 Timing circuits

Abstract

In 3D NAND type memory structures, such as of the BiCS type, the NAND strings have a channel that runs vertically up from the substrate between the memory cells and select gates. In an erase process, holes travel up from the well down at the substrate up towards the bit line in order to reach the cells to be erased. In such a process, the voltage applied to source side select gates should be low enough for the holes to pass through theses gates and up the column, but not so low as to result in device breakdown as the erase voltage is applied to the well. Techniques are presented to do this by controlling the source side select gate voltages so that the difference from the well voltage is kept largely constant during the erase process by use of a fixed offset during ramping and at the final level for the erase process.

Claims

1. A monolithic three-dimensional non-volatile semiconductor memory device, comprising:

a well structure formed in a silicon substrate;

one or more strings each formed along a common channel structure above the well structure and running in a vertical direction relative to the substrate, each of the strings having a plurality of memory cells connected in series between the well structure and a corresponding bit line respectively through source side and drain side select gates, where the memory cells each have a charge storage medium and are arranged in multiple physical levels above the silicon substrate; and

driver circuitry connected to receive a clock signal and connectable to apply voltage levels to the well structure and control gates of the memory cells, the source side select gates, and drain side select gates,

wherein, when performing an erase operation on the strings, the driver circuitry applies to the well structure a first staircase waveform that begins with an initial level and increases in voltage with each of a first number of cycles of the clock signal and, after a delay of a second number of clock cycles subsequent to beginning to apply the first staircase waveform to the well structure, applies the first staircase waveform beginning with the initial level to the control gates of the source side select gates for the remainder of the first number of clock cycles.

2. The monolithic three-dimensional non-volatile semiconductor memory device of claim 1, further comprising:

a plurality of word lines along which the control gates of memory cells are connected and whereby the driver circuitry is connectable thereto, wherein the word lines run in horizontal relative to the substrate;

one or more drain select lines along which the control gates of the source side select gates are connected and whereby the driver circuitry is connectable thereto, wherein the drain select lines run in horizontal relative to the substrate; and

one or more source select lines along which the control gates of the source side select gates are connected and by which the first staircase waveform is applied to the control gates of source side select gates, wherein in the source and drain select lines run in horizontal relative to the substrate.

3. The monolithic three-dimensional non-volatile semiconductor memory device of claim 2, wherein, when performing the erase operation on the strings, the driver circuitry sets the word lines corresponding to memory cells selected for erase to a low voltage level.

4. The monolithic three-dimensional non-volatile semiconductor memory device of claim 3, wherein the low voltage level is ground.

5. The monolithic three-dimensional non-volatile semiconductor memory device of claim 3, wherein the plurality of word lines includes one or more dummy word lines not used for the storage of user data adjacent to one or both of the source side and drain side select lines, wherein when performing the erase operation on the strings, the dummy word lines are set to float.

6. The monolithic three-dimensional non-volatile semiconductor memory device of claim 1, wherein the stings include one or both of multiple source side select gates connected in series and multiple drain side select gates connected in series.

7. The monolithic three-dimensional non-volatile semiconductor memory device of claim 1, further comprising:

a clock connected to the driver circuitry to provide the clock signal thereto.

8. The monolithic three-dimensional non-volatile semiconductor memory device of claim 1, wherein the frequency of the clock signal decreases after a third number of cycles subsequent to beginning to apply the first staircase waveform to the well structure.

9. A method of performing erase operation on a monolithic three-dimensional non-volatile semiconductor memory device, where the memory device includes a well structure formed in a silicon substrate and one or more strings each formed along a common channel structure above the well structure and running in a vertical direction relative to the substrate, each of the strings having a plurality of memory cells connected in series between the well structure and a corresponding bit line respectively through source side and drain side select gates, where the memory cells each have a charge storage medium and are arranged in multiple physical levels above the silicon substrate, the method comprising:

applying to the well structure a first staircase waveform that begins with an initial level and increases in voltage with each of a first number of cycles of the clock signal; and

after a delay of a second number of clock cycles subsequent to beginning to apply the first staircase waveform to the well structure, applying the first staircase waveform beginning with the initial level to the control gates of the source side select gates for the remainder of the first number of clock cycles.

10. The method of claim 9, further comprising:

setting word lines corresponding to memory cells selected for erase to a low voltage level, wherein the word lines run in horizontal relative to the substrate.

11. The method of claim 10, wherein the low voltage level is ground.

12. The method of claim 10, wherein the monolithic three-dimensional non-volatile semiconductor memory device includes one or more dummy word lines not used for the storage of user data adjacent to one or both of the source side and drain side select lines, wherein when performing the erase operation on the strings, the dummy word lines are set to float.

13. The method of claim 9, wherein the stings include one or both of multiple source side select gates connected in series and multiple drain side select gates connected in series.

14. The method of claim 9, wherein the frequency of the clock signal decreases after a third number of cycles subsequent to beginning to apply the first staircase waveform to the well structure.