Word line kick during sensing: trimming and adjacent word lines
First Claim
1. A method of operating a non-volatile memory array formed according to a NAND-type of architecture, comprising:
- performing a sensing operation for memory cells along a selected word line with the word lines of the array biased to a first set of bias conditions, the first set of bias conditions including;
driving the selected word line at a first sensing voltage; and
driving non-selected word lines of the array at a voltage level to allow the memory cells therealong to conduct; and
prior to performing the sensing operation, establishing the first set bias conditions, including;
setting the non-selected word lines to the voltage to allow the memory cells therealong to conduct; and
subsequently raising the selected word line from an initial level to the first sensing voltage, wherein, while selected word line is being raised, the voltage level for a non-selected word line adjacent to the selected word line is lowered from, and then returned to, the voltage to allow the memory cells therealong to conduct.
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Accused Products
Abstract
When applying a sensing voltage at one end of a word line of a non-volatile memory circuit, an initial kick, where the voltage is initially raised somewhat above its final desired voltage, is used. Using on-chip circuitry for the determination of the RC time constant of the word lines allows for this kick to be trimmed to the specifics of the circuit. To further improve settling times for read operations is NAND type architectures, when raising the voltage to the desired read level on a selected word line, a reverse kick, where the non-selected word line'"'"'s voltage is dropped briefly, can be applied to neighboring non-selected word lines.
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Citations
21 Claims
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1. A method of operating a non-volatile memory array formed according to a NAND-type of architecture, comprising:
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performing a sensing operation for memory cells along a selected word line with the word lines of the array biased to a first set of bias conditions, the first set of bias conditions including; driving the selected word line at a first sensing voltage; and driving non-selected word lines of the array at a voltage level to allow the memory cells therealong to conduct; and prior to performing the sensing operation, establishing the first set bias conditions, including; setting the non-selected word lines to the voltage to allow the memory cells therealong to conduct; and subsequently raising the selected word line from an initial level to the first sensing voltage, wherein, while selected word line is being raised, the voltage level for a non-selected word line adjacent to the selected word line is lowered from, and then returned to, the voltage to allow the memory cells therealong to conduct. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. An integrated circuit comprising:
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a plurality of control lines; line driver circuitry for providing line voltage levels; line decoding circuitry connected to the control lines and to the line driver circuitry by which the line voltage levels are selectively applied to the control lines at a first end thereof; a time constant determination circuit connected to the line decoding circuitry for determining time constants for charging by the driver circuitry of the far end, relative to the first end, of the control lines; and on-chip control circuitry connected to the line driver circuitry, the line decoding circuitry, and the time constant determination circuit, whereby when applying a first voltage level to a selected control line, the line driver circuitry initially ramps up the selected control line to a level higher than that the first voltage for a first interval, the duration of the first interval based upon the time constant of the selected control line as determined by the time constant determination circuit. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21)
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Specification