CMOS structures and methods for improving yield

• US 9,318,344 B2
• Filed: 12/01/2014
• Issued: 04/19/2016
• Est. Priority Date: 04/28/2006
• Status: Expired due to Fees

• Current Assignee: Elpis Technologies Inc. (Wi-LAN Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Zhu, Huilong, Yang, Daewon
• Primary Examiner(s): Sofocleous, Alexander
• Assistant Examiner(s): KING, SUN MI KIM
• Application Number:
  US14/556,732
• Publication Number:
  US 20150087121A1
• Time in Patent Office: 505 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823864 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 21/823871 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer

Abstract

A simple, effective and economical method to improved the yield of CMOS devices using contact etching stopper liner, including, single neutral stressed liner, single stressed liner and dual stress liner (DSL), technology is provided. In order to improve the chip yield, the present invention provides a method in which a sputter etching process is employed to smooth/flatten (i.e., thin) the top surface of the contact etch stopper liners. When DSL technology is used, the inventive sputter etching process is used to reduce the complexity caused by DSL boundaries to smooth/flatten top surface of the DSL, which results in significant yield increase. The present invention also provides a semiconductor structure including at least one etched liner.

Claims

1. A method of forming a semiconductor structure comprising:

forming a first transistor of a first polarity laterally separated from a second transistor of a second polarity different than the first polarity over a semiconductor substrate;

forming a first stressed layer having a first stress located over the first transistor and a second stressed layer having a second stress different from the first stress and located over the first transistor and the second transistor, said second stressed layer having a deposited thickness over the second transistor, and where the first stressed layer and the second stressed layer abut and overlap each other in an area between the first and second transistors and defining an overlap area having an overlap thickness, said overlap area is located above an isolation structure; and

sputter etching said second stressed layer to provide an etched second stressed layer that has an etched thickness over the second transistor that is less than said deposited thickness, and said etched second stressed layer over said second transistor has tapered surface sidewalls that meet each other, and wherein said overlap thickness has been reduced and said etched second stressed layer in said overlap area has tapered surface sidewalls that meet each other.

2. The method of claim 1 further comprising forming a stressed neutral layer atop at least the etched second stressed layer.

3. The method of claim 1 further comprising forming an interlevel dielectric having contact vias located therein atop said semiconductor substrate, said first stressed layer, and said etched second stressed layer.

4. The method of claim 1 wherein said sputter etching is performed in a plasma comprising an inert gas and nitrogen.

5. The method of claim 1 wherein said sputter etching is performed at a plasma power from about 800 to about 3000 Watts.

6. A method of forming a semiconductor structure comprising:

forming a first transistor of a first polarity laterally separated from a second transistor of a second polarity different from the first polarity over a semiconductor substrate, wherein at least one dummy gate is located on a surface of an isolation region in said substrate between said first and second transistors;

forming a first stressed layer having a first stress located over the first transistor and a second stressed layer having a second stress different from the first stress located over the first stressed layer and the second transistor, said second stressed layer having a deposited thickness over the second transistor, where the first stressed layer and the second stressed layer abut and overlap each other in an area between the first and second transistors defining an overlap area having an overlap thickness; and

sputter etching said second stressed layer to provide an etched second stressed layer having an etched thickness that is less than said deposited thickness over the second transistor and said etched second stressed layer over said second transistor has tapered surface sidewalls that meet each other, and wherein said overlap thickness has been reduced and said etched second stressed layer in said overlap area has tapered surface sidewalls that meet each other.

7. The method of claim 6 wherein said sputter etching is performed in a plasma comprising an inert gas and nitrogen.

8. The method of claim 6 wherein said sputter etching is performed at a plasma power from about 800 to about 3000 Watts.

9. The method of claim 6 further comprising forming a stressed neutral layer atop said first stress layer said second etch stressed layer.

10. The method of claim 6 further comprising forming an interlevel dielectric material having contact vias located therein atop said semiconductor substrate, said first stress layer and said second stressed layer.

11. The method of claim 6 wherein said tapered surface sidewalls over said first transistor meet each other forming an inverted V-shape.

12. The method of claim 6 wherein said tapered surface sidewalls over said second transistor meet each other forming an inverted V-shape.

13. The method of claim 6 wherein said tapered surface sidewalls over said overlap area meet each other forming an inverted V-shape.