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CMOS structures and methods for improving yield

  • US 9,318,344 B2
  • Filed: 12/01/2014
  • Issued: 04/19/2016
  • Est. Priority Date: 04/28/2006
  • Status: Expired due to Fees
First Claim
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1. A method of forming a semiconductor structure comprising:

  • forming a first transistor of a first polarity laterally separated from a second transistor of a second polarity different than the first polarity over a semiconductor substrate;

    forming a first stressed layer having a first stress located over the first transistor and a second stressed layer having a second stress different from the first stress and located over the first transistor and the second transistor, said second stressed layer having a deposited thickness over the second transistor, and where the first stressed layer and the second stressed layer abut and overlap each other in an area between the first and second transistors and defining an overlap area having an overlap thickness, said overlap area is located above an isolation structure; and

    sputter etching said second stressed layer to provide an etched second stressed layer that has an etched thickness over the second transistor that is less than said deposited thickness, and said etched second stressed layer over said second transistor has tapered surface sidewalls that meet each other, and wherein said overlap thickness has been reduced and said etched second stressed layer in said overlap area has tapered surface sidewalls that meet each other.

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