Semiconductor storage device comprising peripheral circuit, Shielding layer, and memory cell array

• US 9,318,374 B2
• Filed: 09/07/2012
• Issued: 04/19/2016
• Est. Priority Date: 09/21/2011
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Atsumi, Tomoaki, Okuda, Takashi
• Primary Examiner(s): Pert, Evan
• Assistant Examiner(s): Hillman, Damon
• Application Number:
  US13/606,472
• Publication Number:
  US 20130069132A1
• Time in Patent Office: 1,320 Days
• Field of Search: 257/301
• US Class Current: 1/1
• CPC Class Codes: H01L 21/76801 characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
• CPC Class Codes: H01L 21/76826 by contacting the layer with gases, liquids or plasmas
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/1207 combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 29/16 including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H10B 12/03 Making the capacitor or connections thereto
• CPC Class Codes: H10B 12/05 Making the transistor
• CPC Class Codes: H10B 12/30 DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
• CPC Class Codes: H10B 12/50 Peripheral circuit region structures
• CPC Class Codes: H10B 20/00 Read-only memory [ROM] devices
• CPC Class Codes: H10B 41/70 the floating gate being an electrode shared by two or more components

Abstract

Probability of malfunction of a semiconductor storage device is reduced. A shielding layer is provided between a memory cell array (e.g., a memory cell array including a transistor formed using an oxide semiconductor material) and a peripheral circuit (e.g., a peripheral circuit including a transistor formed using a semiconductor substrate), which are stacked. With this structure, the memory cell array and the peripheral circuit can be shielded from radiation noise generated between the memory cell array and the peripheral circuit. Thus, probability of malfunction of the semiconductor storage device can be reduced.

Claims

1. A semiconductor storage device comprising:

a peripheral circuit;

a conductive film over the peripheral circuit; and

a memory cell array over the conductive film,

wherein the memory cell array comprises a memory cell comprising a transistor, and

wherein entirety of the memory cell array overlaps with the conductive film.

2. The semiconductor storage device according to claim 1, wherein an active layer of the transistor comprises an oxide semiconductor material.

3. The semiconductor storage device according to claim 1, wherein the peripheral circuit is formed by utilizing a semiconductor substrate.

4. The semiconductor storage device according to claim 1, further comprising a second conductive film over the memory cell array and a second memory cell array over the second conductive film.

5. The semiconductor storage device according to claim 1, wherein the conductive film is configured to be supplied with a ground potential.

6. The semiconductor storage device according to claim 5, wherein the peripheral circuit is electrically connected to the memory cell array through a contact plug comprising a same layer as the conductive film.

7. A semiconductor storage device comprising:

a peripheral circuit;

a shielding layer over the peripheral circuit; and

a memory cell array over the shielding layer,

wherein the memory cell array comprises a memory cell comprising a transistor,

wherein the shielding layer is configured to shield the peripheral circuit and the memory cell array from radiation noise generated between the peripheral circuit and the memory cell array, and

wherein the shielding layer is configured to be supplied with a ground potential.

8. The semiconductor storage device according to claim 7, wherein an active layer of the transistor comprises an oxide semiconductor material.

9. The semiconductor storage device according to claim 7, wherein the peripheral circuit is formed by utilizing a semiconductor substrate.

10. The semiconductor storage device according to claim 7, further comprising a second shielding layer over the memory cell array and a second memory cell array over the second shielding layer.

11. The semiconductor storage device according to claim 7, wherein entirety of the memory cell array overlaps with the shielding layer.

12. The semiconductor storage device according to claim 7, wherein the peripheral circuit is electrically connected to the memory cell array through a contact plug comprising a same layer as the shielding layer.

13. A semiconductor storage device comprising:

a peripheral circuit;

a first insulating film over the peripheral circuit;

a conductive film over the first insulating film;

a second insulating film over the conductive film; and

a memory cell array over the second insulating film,

wherein the memory cell array comprises a memory cell comprising a transistor electrically connected to an electrode,

wherein a capacitor is formed using a region of the conductive film as a first electrode, a region of the second insulating film over the region of the conductive film, and a region of the electrode over the region of the second insulating film as a second electrode, and

wherein entirety of the memory cell array overlaps with the conductive film.

14. The semiconductor storage device according to claim 13, wherein an active layer of the transistor comprises an oxide semiconductor material.

15. The semiconductor storage device according to claim 13, wherein the peripheral circuit is formed by utilizing a semiconductor substrate.

16. The semiconductor storage device according to claim 13, further comprising a second conductive film over the memory cell array and a second memory cell array over the second conductive film.

17. The semiconductor storage device according to claim 13, wherein the conductive film is configured to be supplied with a ground potential.

18. The semiconductor storage device according to claim 17, wherein the peripheral circuit is electrically connected to the memory cell array through a contact plug comprising a same layer as the conductive film.

19. The semiconductor storage device according to claim 13, wherein a distance between the region of the electrode and the region of the conductive film is shorter than a distance between at least one of a source and a drain of the transistor and the conductive film.

20. The semiconductor storage device according to claim 13, wherein the capacitor is a trench capacitor formed in a depressed portion or an opening portion provided in the first insulating film.