Method for manufacturing semiconductor device including a MOS-type transistor

• US 9,318,391 B2
• Filed: 01/16/2015
• Issued: 04/19/2016
• Est. Priority Date: 03/09/2010
• Status: Active Grant

• Current Assignee: LAPIS Semiconductor Co., Ltd. (ROHM Co., Ltd.)
• Original Assignee: LAPIS Semiconductor Co., Ltd. (ROHM Co., Ltd.)
• Inventors: Arai, Yasuo, Okihara, Masao, Kasai, Hiroki
• Primary Examiner(s): Nguyen, Khiem D
• Application Number:
  US14/598,364
• Publication Number:
  US 20150126002A1
• Time in Patent Office: 459 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/225 using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer H01L21/221 - H01L21/222 take precedence
• CPC Class Codes: H01L 21/2652 Through-implantation
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 27/1207 combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
• CPC Class Codes: H01L 27/1443 with at least one potential jump or surface barrier
• CPC Class Codes: H01L 27/1461 characterised by the photosensitive area
• CPC Class Codes: H01L 27/14612 involving a transistor
• CPC Class Codes: H01L 27/14658 X-ray, gamma-ray or corpuscular radiation imagers measuring X-, gamma- or corpuscular radiation G01T1/00
• CPC Class Codes: H01L 29/66477 with an insulated gate, i.e. MISFET
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel
• CPC Class Codes: H01L 29/8611 Planar PN junction diodes

Abstract

There is provided a semiconductor device and a method for manufacturing a semiconductor device. Within the N-type semiconductor layer formed from a high resistance N-type substrate, the P-type well diffusion layer and P-type extraction layer are formed and are fixed to ground potential. Due thereto, a depletion layer spreading on the P-type well diffusion layer side does not reach the interlayer boundary between the P-type well diffusion layer and the buried oxide film. Hence, the potential around the surface of the P-type well diffusion layer is kept at a ground potential. Accordingly, when the voltages are applied to the backside of the N-type semiconductor layer and a cathode electrode, a channel region at the MOS-type semiconductor formed as a P-type semiconductor layer is not activated. Due thereto, leakage current that may occur independently of a control due to the gate electrode of a transistor can be suppressed.

Claims

1. A method for manufacturing a semiconductor device comprising:

laminating an oxide film layer and a semiconductor layer of a first-conductive-type on a semiconductor layer of a second-conductive-type in order;

forming an active region of the first-conductive-type in the semiconductor layer of the first-conductive-type;

forming an insulating film on the semiconductor layer of the first-conductive-type;

forming a first region of the first-conductive-type by diffusing, based on a position of the active region of the first-conductive-type, an impurity of the first-conductive-type within a first region of the semiconductor layer of the second-conductive-type that includes a lower portion of the active region of the first-conductive-type;

forming a MOS-type transistor in the active region of the first-conductive-type;

removing the oxide film layer from a predetermined region, the predetermined region being a region of the semiconductor layer of the first-conductive-type in which a first electrode, a second electrode and a third electrode are to be formed;

forming, in the first region of the first-conductive-type, a second region of the first-conductive-type by diffusing the impurity of the first-conductive-type within the predetermined region from which the oxide film layer has been removed and on which the first electrode is to be formed and, forming a third region of the first-conductive-type by diffusing the impurity of the first-conductive-type within the predetermined region on which the third electrode is to be formed;

forming a region of the second-conductive-type by diffusing an impurity of the second-conductive-type within the predetermined region from which the oxide film layer has been removed and in which the second electrode is to be formed; and

forming the first electrode, the second electrode and the third electrode.

2. The method for manufacturing the semiconductor device according to claim 1, further comprising:

forming, between the process of forming the insulating film and the process of forming the first first-conductive-type region, a second region of the second-conductive-type by diffusing, based on the position of the active region of the first-conductive-type, the impurity of the second-conductive-type within a first region of the semiconductor layer of the second-conductive-type including a lower portion of the active region of the first-conductive-type.

3. The method for manufacturing the semiconductor device according to claim 1, further comprising:

forming a ground electrode to which the first electrode and the second electrode are connected; and

forming a voltage applying unit for applying voltage to a surface of the semiconductor layer of the second-conductive-type opposite to a surface on which the first region of the first-conductive-type is formed and the second electrode, in order to deplete the semiconductor layer of the second-conductive-type.

4. The method for manufacturing the semiconductor device according to claim 1, wherein the first-conductive-type is p-type and the second-conductive-type is n-type.

5. The method for manufacturing the semiconductor device according to claim 1, wherein the semiconductor layer of the first-conductive-type and the semiconductor layer of the second-conductive-type have a specific resistance of 10 ohm-centimeters (Ω

·

cm).

6. The method for manufacturing the semiconductor device according to claim 1, wherein the oxide film layer comprises silicon dioxide (SiO₂).