Semiconductor structure and manufacturing method thereof

• US 9,318,490 B2
• Filed: 01/13/2014
• Issued: 04/19/2016
• Est. Priority Date: 01/13/2014
• Status: Active Grant

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Tsao, Po-Chao, Huang, Yao-Hung, Lin, Chien-Ting, Wei, Ming-Te
• Primary Examiner(s): Cao, Phat X
• Assistant Examiner(s): Vieira, Diana C
• Application Number:
  US14/153,079
• Publication Number:
  US 20150200192A1
• Time in Patent Office: 827 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/32115 Planarisation
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/82345 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/823456 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 21/823828 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/82385 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 27/0922 Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS

Abstract

The present invention provides a semiconductor structure, including a substrate, having a dielectric layer disposed thereon, a first device region and a second device region defined thereon, at least one first trench disposed in the substrate within the first device region, at least one second trench and at least one third trench disposed in the substrate within the second device region, a work function layer, disposed in the second trench and the third trench, wherein the work function layer partially covers the sidewall of the second trench, and entirely covers the sidewall of the third trench, and a first material layer, disposed in the second trench and the third trench, wherein the first material layer covers the work function layer disposed on partial sidewall of the second trench, and entirely covers the work function layer disposed on the sidewall of the third trench.

Claims

1. A method for forming a semiconductor structure, at least comprising the following steps:

providing a substrate, having a dielectric layer disposed thereon, a first device region and a second device region defined thereon;

forming at least one first trench in the dielectric layer within the first device region, at least one second trench and at least one third trench in the substrate within the second device region;

forming a first work function layer in the first trench, the second trench and the third trench;

forming a plurality of first material layers in the first trench, the second trench and the third trench, wherein the first material layer covers parts of the first work function layer disposed in the first trench and disposed on the sidewall of the second trench, and entirely covers the first work function layer disposed on the sidewall of the third trench;

forming a second material layer to fill the first trench and the second trench after the first material layer is formed;

removing the first material layer and the second material layer in the first trench;

removing the second material layer in the second trench; and

removing the first work function layer in the first trench entirely, and removing a partial first work function layer disposed in the second trench.

2. The method of claim 1, further comprising forming a high-k layer in the first trench, the second trench and the third trench.

3. The method of claim 1, after the first work function layer in the second trench is partially removed, further comprising forming a second work function layer and a conductive layer in the first trench, the second trench and the third trench.

4. The method of claim 3, after the second work function layer and the conductive layer is formed, further comprising performing a planarization process.

5. The method of claim 1, wherein the material of the first material layer comprises organo-siloxane.

6. The method of claim 1, wherein the material of the second material layer comprises polymer.

7. The method of claim 1, wherein a bottom of the third trench is wider than a bottom of the second trench.

8. The method of claim 1, wherein the first material layer and the second material layer have different etching selectivity.