Method of fabricating semiconductor device having grooved source contact region

• US 9,318,566 B2
• Filed: 01/21/2014
• Issued: 04/19/2016
• Est. Priority Date: 03/27/2013
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Suk-Kyun, Lee, Eung-Kyu
• Primary Examiner(s): FERNANDES, ERROL V
• Application Number:
  US14/159,940
• Publication Number:
  US 20140295632A1
• Time in Patent Office: 819 Days
• Field of Search: 257/330, 257/334, 438/270
• US Class Current: 1/1
• CPC Class Codes: H01L 29/0869 Shape cell layout H01L29/0696
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42356 Disposition, e.g. buried gate electrode H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

In a method of fabricating a semiconductor device, a channel layer is formed on a substrate, and trench patterns are formed in the channel layer. Impurity bodies are formed in the channel layer between the trench patterns, and grooves are formed between the trench patterns in the impurity bodies formed in the channel layer. Source isolation regions are formed in the impurity bodies at bottom portions of the grooves, and source regions are formed in the impurity bodies at sidewall portions of the grooves.

Claims

1. A method of fabricating a semiconductor device, comprising:

forming a channel layer on a substrate;

forming trench patterns in the channel layer;

forming impurity bodies in the channel layer between the trench patterns;

forming grooves in the impurity bodies formed in the channel layer;

forming source isolation regions in the impurity bodies at bottom portions of the grooves; and

forming source regions in the impurity bodies at sidewall portions of the grooves,

wherein the source isolation regions directly contact the source regions on either side of the sidewall portions of the grooves;

wherein the forming of the trench patterns comprises forming cell trench patterns, and

the forming of the cell trench patterns comprises;

forming cell trenches in the channel layer;

forming cell shield patterns in lower portions of the cell trenches;

forming cell gate patterns on the cell shield patterns positioned within the cell trenches; and

forming cell capping patterns on the cell gate patterns positioned within the cell trenches;

wherein the forming of the cell shield patterns comprises;

conformally forming a preliminary cell shield insulating layer on inner walls of the cell trenches;

forming a preliminary cell shield electrode on the preliminary cell shield insulating layer to fill the cell trenches;

recessing the preliminary cell shield electrode to form a cell shield electrode having a top surface disposed in the middle region of the cell trench; and

recessing the preliminary cell shield insulating layer to form a cell shield insulating layer to expose upper portions of the inner walls of the cell trenches and having a top surface disposed at a lower level than the top surface of the cell shield electrode;

wherein the forming of the cell gate patterns comprises;

forming a cell gate insulating layer on the top surface of the cell shield electrode and the inner walls of the cell trenches;

forming a preliminary cell gate electrode on the cell gate insulating layer to fill the cell trenches; and

recessing the preliminary cell gate electrode to form a cell gate electrode having a top surface disposed in the middle of the cell trench; and

wherein the forming of the cell capping pattern comprises;

forming a cell buffer layer on the top surface of the cell gate electrode;

forming a cell capping stopper layer on the cell buffer layer and the inner walls of the cell trenches;

forming a preliminary cell capping layer on the cell capping stopper layer to fill the cell trenches; and

planarizing the preliminary cell capping layer to a cell capping layer, so that the cell capping layer remains only within the cell trenches.

2. The method of claim 1, wherein the forming of the channel layer comprises:

forming a lower channel layer on the substrate using an epitaxial growth process, and forming an upper channel layer on the lower channel layer using an epitaxial growth process,

wherein the substrate comprises phosphorus (P) at a first concentration, the lower channel layer comprises arsenic (As) at a second concentration lower than the first concentration, and the upper channel layer comprises phosphorus at a third concentration lower than the first concentration and higher than the second concentration.

3. The method of claim 1, wherein the forming of the trench patterns further comprises forming a shield pickup trench pattern, and

the forming of the shield pickup trench patterns comprises:

forming a shield pickup trench in the channel layer to have a greater width and a greater depth than the cell trench,

forming a shield pickup insulating layer on an inner wall of the shield pickup trench; and

forming a shield pickup electrode on the shield pickup insulating layer to fill the shield pickup trench,

wherein a top surface of the shield pickup electrode is co-planar with, or at a higher level than, a top surface of the channel layer.

4. The method of claim 1, wherein:

the cell capping stopper layer includes silicon nitride,

the cell capping layer includes silicon oxide, and

a top surface of the cell capping layer is co-planar with, or at a higher level than, the top surface of the channel layer.

5. The method of claim 1, wherein each of the cell gate patterns has a greater horizontal width than each of the cell shield patterns.

6. The method of claim 1, wherein sidewall portions of the grooves are inclined,

the forming of the source isolation regions comprises implanting P-type impurities along profiles of the bottom portions and sidewall portions of the grooves, and

the forming of the source regions comprises obliquely implanting N-type impurities under the sidewall portions of the grooves to inverse the source isolation regions disposed under the sidewall portions of the grooves from a P type to an N type.

7. The method of claim 1, further comprising:

conformally forming a preliminary barrier metal on the bottom and sidewall portions of the grooves;

forming a preliminary source electrode metal on the preliminary barrier metal to fill the grooves; and

planarizing the preliminary source electrode metal.

8. A method of fabricating a semiconductor device, comprising:

forming a channel layer on a substrate;

forming trench patterns in the channel layer;

forming impurity bodies in the channel layer between the trench patterns;

forming grooves in the impurity bodies formed in the channel layer;

after forming the grooves, implanting impurities in the impurity bodies exposed by the grooves to form source isolation regions in the impurity bodies at bottom portions of the grooves; and

after forming the source isolation regions, implanting impurities in the impurity bodies exposed by the grooves to form source regions in the impurity bodies at sidewall portions of the grooves.

9. The method of claim 8, wherein the forming of the channel layer comprises:

forming a lower channel layer on the substrate using an epitaxial growth process, and forming an upper channel layer on the lower channel layer using an epitaxial growth process,

wherein the substrate comprises phosphorus (P) at a first concentration, the lower channel layer comprises arsenic (As) at a second concentration lower than the first concentration, and the upper channel layer comprises phosphorus at a third concentration lower than the first concentration and higher than the second concentration.

10. The method of claim 8, wherein the forming of the trench patterns comprises forming cell trench patterns, and

the forming of the cell trench patterns comprises:

forming cell trenches in the channel layer;

forming cell shield patterns in lower portions of the cell trenches;

forming cell gate patterns on the cell shield patterns positioned within the cell trenches; and

forming cell capping patterns on the cell gate patterns positioned within the cell trenches.

11. The method of claim 10, wherein the forming of the trench patterns further comprises forming a gate pickup trench pattern, and

the forming of the gate trench patterns comprises:

forming a gate pickup trench in the channel layer to have a greater width and a greater depth than the cell trench,

forming a gate pickup shield pattern in a lower portion of the gate pickup trench; and

forming a gate pickup pattern on the gate pickup shield pattern disposed in the gate pickup trench,

wherein a top surface of the gate pickup pattern is co-planar with, or at a higher level than, a top surface of the channel layer.

12. The method of claim 11, wherein the forming of the gate pickup shield pattern comprises:

conformally forming a preliminary gate pickup shield insulating layer on inner walls of the gate pickup trenches;

forming a preliminary gate pickup shield electrode on the preliminary gate pickup shield insulating layer to fill the gate pickup trenches;

recessing the preliminary gate pickup shield electrode to form a gate pickup shield electrode having a top surface disposed in a middle region of the gate pickup trench; and

recessing the preliminary gate pickup shield insulating layer to form a gate pickup shield insulating layer exposing upper portions of the inner walls of the gate pickup trenches and having a top surface disposed at a lower level than the top surface of the gate pickup shield electrode.

13. The method of claim 12, wherein the forming of the gate pickup pattern comprises:

forming a gate pickup insulating layer on the top surface of the gate pickup shield electrode and the inner walls of the gate pickup trenches;

forming a preliminary gate pickup electrode on the gate pickup insulating layer to fill the gate pickup trench; and

recessing the preliminary gate pickup electrode to form a gate pickup electrode having a top surface disposed in the middle of the gate pickup trench.

14. The method of claim 10, wherein the forming of the trench patterns further comprises forming a shield pickup trench pattern, and

the forming of the shield pickup trench patterns comprises:

forming a shield pickup trench in the channel layer to have a greater width and a greater depth than the cell trench,

forming a shield pickup insulating layer on an inner wall of the shield pickup trench; and

forming a shield pickup electrode on the shield pickup insulating layer to fill the shield pickup trench,

wherein a top surface of the shield pickup electrode is co-planar with, or at a higher level than, a top surface of the channel layer.

15. The method of claim 10, wherein the forming of the cell shield patterns comprises:

conformally forming a preliminary cell shield insulating layer on inner walls of the cell trenches;

forming a preliminary cell shield electrode on the preliminary cell shield insulating layer to fill the cell trenches;

recessing the preliminary cell shield electrode to form a cell shield electrode having a top surface disposed in the middle region of the cell trench; and

recessing the preliminary cell shield insulating layer to form a cell shield insulating layer to expose upper portions of the inner walls of the cell trenches and having a top surface disposed at a lower level than the top surface of the cell shield electrode.

16. The method of claim 15, wherein the forming of the cell gate patterns comprises:

forming a cell gate insulating layer on the top surface of the cell shield electrode and the inner walls of the cell trenches;

forming a preliminary cell gate electrode on the cell gate insulating layer to fill the cell trenches; and

recessing the preliminary cell gate electrode to form a cell gate electrode having a top surface disposed in the middle of the cell trench.

17. The method of claim 16, wherein the forming of the cell capping pattern comprises:

forming a cell buffer layer on the top surface of the cell gate electrode;

forming a cell capping stopper layer on the cell buffer layer and the inner walls of the cell trenches;

forming a preliminary cell capping layer on the cell capping stopper layer to fill the cell trenches; and

planarizing the preliminary cell capping layer to form a cell capping layer, so that the cell capping layer remains only within the cell trenches.

18. The method of claim 10, wherein each of the cell gate patterns has a greater horizontal width than each of the cell shield patterns.

19. The method of claim 8, wherein sidewall portions of the grooves are inclined,

the forming of the source isolation regions comprises implanting P-type impurities along profiles of the bottom portions and sidewall portions of the grooves, and

the forming of the source regions comprises obliquely implanting N-type impurities under the sidewall portions of the grooves to inverse the source isolation regions disposed under the sidewall portions of the grooves from a P type to an N type.

20. The method of claim 8, further comprising:

conformally forming a preliminary barrier metal on the bottom and sidewall portions of the grooves;

forming a preliminary source electrode metal on the preliminary barrier metal to fill the grooves; and

planarizing the preliminary source electrode metal.