Low voltage embedded memory having cationic-based conductive oxide element

• US 9,318,701 B2
• Filed: 11/02/2015
• Issued: 04/19/2016
• Est. Priority Date: 11/27/2012
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Karpov, Elijah V., Doyle, Brian S., Kuo, Charles C., Chau, Robert S.
• Primary Examiner(s): Byrne, Harry W
• Application Number:
  US14/930,393
• Publication Number:
  US 20160056374A1
• Time in Patent Office: 169 Days
• Field of Search: 365/46, 365/94, 365/100, 365/113, 365/129, 365/148, 365/163, 257 2- 5, 257/9, 257/296, 257/310, 257/E21.35, 257/E31.047, 257/E27.006, 438/29, 438/95, 438/96, 438/166, 438/135, 438/240, 438/785, 438/259, 438/365, 438/482, 438/486, 438/597, 977/754
• US Class Current: 1/1
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/0011 comprising conductive bridging RAM [CBRAM] or programming metallization cells [PMCs]
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 2013/0073 Write using bi-directional cell biasing
• CPC Class Codes: G11C 2213/79 Array wherein the access device being a transistor
• CPC Class Codes: H10B 63/30 comprising selection components having three or more electrodes, e.g. transistors
• CPC Class Codes: H10N 70/245 the species being metal cations, e.g. programmable metallization cells
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/8416 adapted for supplying ionic species
• CPC Class Codes: H10N 70/8822 Sulfides, e.g. CuS
• CPC Class Codes: H10N 70/883 Oxides or nitrides
• CPC Class Codes: H10N 70/8833 Binary metal oxides, e.g. TaOx
• CPC Class Codes: H10N 70/8836 Complex metal oxides, e.g. perovskites, spinels

Abstract

Low voltage embedded memory having cationic-based conductive oxide elements is described. For example, a material layer stack for a memory element includes a first conductive electrode. A cationic-based conductive oxide layer is disposed on the first conductive electrode. The cationic-based conductive oxide layer has a plurality of cation vacancies therein. A second electrode is disposed on the cationic-based conductive oxide layer.

Claims

1. A non-volatile memory device, comprising:

a first conductive electrode;

a cationic-based conductive oxide layer disposed on the first conductive electrode; and

a second electrode disposed on the cationic-based conductive oxide layer;

a transistor electrically connected to the first or the second electrode, a source line, and a word line; and

a bit line electrically coupled with the other of the first or the second electrode.

2. The non-volatile memory device of claim 1, wherein the cationic-based conductive oxide layer has a plurality of cation vacancies therein.

3. The non-volatile memory device of claim 1, wherein the cationic-based conductive oxide layer comprises a material having cation-based mobility.

4. The non-volatile memory device of claim 3, wherein the material having cation-based mobility has lithium (Li⁺), sodium (Na⁺) or silver (Ag⁺) mobility.

5. The non-volatile memory device of claim 4, wherein the material having cation-based mobility has lithium (Li⁺) mobility and is selected from the group consisting of LiCoO₂, LiMnO₂, Li₄TiO₁₂, LiNiO₂, LiNbO₃, Li₃N:

H and LiTiS₂.

6. The non-volatile memory device of claim 4, wherein the material having cation-based mobility has sodium (Na⁺) mobility and is Na β

-alumina.

7. The non-volatile memory device of claim 4, wherein the material having cation-based mobility has silver (Ag⁺) mobility and is selected from the group consisting of AgI, RbAg₄I₅ and AgGeAsS₃.

8. The non-volatile memory device of claim 1, wherein the resistivity of the cationic-based conductive oxide layer is approximately in the range of 10 mOhm cm-10 kOhm when measured at a low field of approximately 0.1V.

9. The non-volatile memory device of claim 1, wherein the second electrode comprises a material that is an intercalation host for cations.

10. The non-volatile memory device of claim 9, wherein the material is selected from the group consisting of graphite and a metal chalcogenide.

11. The non-volatile memory device of claim 1, wherein the first electrode is a noble metal electrode.

12. The non-volatile memory device of claim 11, wherein the noble metal electrode comprises a material selected from the group consisting of palladium (Pd) and platinum (Pt).

13. A method of operating a non-volatile memory device, the comprising:

applying a positive bias to a memory element, the memory element comprising a first conductive electrode, a cationic-based conductive oxide layer disposed on the first conductive electrode, and a second electrode disposed on the cationic-based conductive oxide layer; and

changing the cationic-based conductive oxide layer from a more conductive state to a less conductive state by the applying.

14. The method of claim 13, wherein the cationic-based conductive oxide layer includes lithium atoms and lithium vacancies, and wherein changing the cationic-based conductive oxide layer from the more conductive state to the less conductive state comprises migrating the lithium atoms from one of the electrodes toward the bulk of the cationic-based conductive oxide layer.

15. The method of claim 13, wherein changing the cationic-based conductive oxide layer from the more conductive state to the less conductive state comprises causing a change in composition of the cationic-based conductive oxide layer.

16. The method of claim 13, wherein applying the positive bias comprises applying a bias of less than absolute 1V.

17. A method of operating a non-volatile memory device, the comprising:

applying a negative bias to a memory element, the memory element comprising a first conductive electrode, a cationic-based conductive oxide layer disposed on the first conductive electrode, and a second electrode disposed on the cationic-based conductive oxide layer; and

changing the cationic-based conductive oxide layer from a less conductive state to a more conductive state by the applying.

18. The method of claim 17, wherein the cationic-based conductive oxide layer includes lithium atoms and lithium vacancies, and wherein changing the cationic-based conductive oxide layer from the less conductive state to the more conductive state comprises migrating the lithium atoms from the bulk of the cationic-based conductive oxide layer toward one of the electrodes.

19. The method of claim 17, wherein changing the cationic-based conductive oxide layer from the less conductive state to the more conductive state comprises causing a change in composition of the cationic-based conductive oxide layer.

20. The method of claim 17, wherein applying the negative bias comprises applying a bias of less than absolute 1V.