Operational amplifier input offset correction with transistor threshold voltage adjustment

• US 9,319,013 B2
• Filed: 08/19/2014
• Issued: 04/19/2016
• Est. Priority Date: 08/19/2014
• Status: Active Grant

• Current Assignee: Fujitsu Semiconductor Limited (Fujitsu Limited)
• Original Assignee: Fujitsu Semiconductor Limited (Fujitsu Limited)
• Inventors: Kuo, Augustine
• Primary Examiner(s): Nguyen, Patricia T
• Application Number:
  US14/463,568
• Publication Number:
  US 20160056780A1
• Time in Patent Office: 609 Days
• Field of Search: 330/261, 330/9
• US Class Current: 1/1
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate
• CPC Class Codes: H03F 1/0272 by using a signal derived from the output signal
• CPC Class Codes: H03F 2203/45112 the biasing of the differential amplifier being controlled from the input or the output signal
• CPC Class Codes: H03F 2203/45214 Offset in a differential amplifier being reduced by control of the substrate voltage, the voltage being either fixed or variable
• CPC Class Codes: H03F 2203/45342 the AAC comprising control means on a back gate of the AAC
• CPC Class Codes: H03F 2203/45674 the LC comprising one current mirror
• CPC Class Codes: H03F 3/45 Differential amplifiers differential sense amplifiers G11C7/062
• CPC Class Codes: H03F 3/45179 using MOSFET transistors as the active amplifying circuit H03F3/45278 takes precedence
• CPC Class Codes: H03F 3/45183 Long tailed pairs H03F3/4521, H03F3/45237 take precedence
• CPC Class Codes: H03F 3/45901 using switching means, e.g. sample and hold

Abstract

A device can include an operational amplifier (op amp) circuit having a differential transistor pair, a first transistor of the differential transistor pair being formed in a first well of a substrate and a second transistor of the differential transistor pair being formed in a second well of the substrate; a body bias generator configured to generate at least a first body bias voltage for the first well, and not the second well, that varies in response to a first body bias control value; and a control circuit configured to selectively generate the first body bias control value in response to an input offset voltage of the op amp.

Claims

1. A device, comprising:

an operational amplifier (op amp) circuit having a differential transistor pair, a first transistor of the differential transistor pair being formed in a first well of a substrate and a second transistor of the differential transistor pair being formed in a second well of the substrate;

a body bias generator configured to generate at least a first body bias voltage for the first well, and not the second well, that varies in response to a first body bias control value; and

a control circuit configured to selectively generate the first body bias control value in response to an input offset voltage of the op amp.

2. The device of claim 1, wherein:

the first transistor has a gate coupled to a positive (+) input of the op amp and the second transistor has a gate coupled to a negative (−

) input of the op amp.

3. The device of claim 1, wherein:

the body bias generator includes

a first body bias generator configured to generate the first body bias voltage for the first well, and

a second body bias generator configured to generate a second body bias voltage for the second well that varies in response to a second body bias control value; and

the control circuit is configured to selectively generate the second body bias control value in response to the input offset voltage of the op amp.

4. The device of claim 1, wherein:

the control circuit comprises

an op amp control circuit configured to apply a common voltage to positive (+) and negative (−

) inputs of the op amp, and

a sampling circuit configured to measure an output voltage of the op amp as the common voltage is applied to the (+) and (−

) inputs of the op amp.

5. The device of claim 1, wherein:

the differential transistor pair has a conductivity type selected from the group of;

n-channel transistors and p-channel transistors.

6. The device of claim 1, wherein:

the differential transistor pair comprise deeply depleted channel (DDC) transistors, each DDC transistor having a screening region formed below a substantially undoped channel, the screening region including a dopant concentration of no less than 1×

10¹⁸ dopant atoms/cm³ with dopants of a conductivity type opposite to that of a source and drain of the DDC transistor.

7. A device, comprising:

an operational amplifier (op amp) circuit having a transistor pair of the same conductivity type, a first transistor of the pair being formed in a first well and operational in a sensing of a voltage at a positive (+) input of the op amp, and a second transistor of the pair being formed in second well and operational in a sensing of a voltage applied at a negative (−

) input of the op amp;

a body bias generator configured to vary a first body bias voltage applied to the first well, and not the second well, that varies in response to a first body bias control value; and

a control circuit configured to selectively generate the first body bias control value in response to an input offset voltage of the op amp.

8. The device of claim 7, wherein:

the first transistor is a first transistor of a differential pair, having a gate coupled to the (+) input, and

the second transistor is a second transistor of the differential pair, having a gate coupled to the (−

) input.

9. The device of claim 7, wherein:

the op amp further includes

a differential transistor pair comprising a first input transistor having a gate coupled to the (+) input and a second input transistor having a gate coupled the (−

) input, and

the first and second transistors form part of an active load for the differential transistor pair, the first transistor being coupled to the first input transistor and the second transistor being coupled to the second input transistor.

10. The device of claim 7, wherein:

the control circuit comprises an offset sampling circuit configured to sample the input offset voltage of the op amp.

11. The device of claim 7, wherein:

the control circuit comprises a compare circuit configured to compare an offset value corresponding to the input offset voltage of the op amp with a target voltage.

12. The device of claim 7, wherein:

the body bias generator includes

a first body bias generator configured to generate the first body bias voltage for the first well, and

a second body bias generator configured to generate a second body bias voltage for the second well that varies in response to a second body bias control value; and

the control circuit is configured to selectively generate the second body bias control value in response to the input offset voltage of the op amp.

13. The device of claim 7, wherein:

the transistor pair comprise deeply depleted channel (DDC) transistors, each DDC transistor having a screening region formed below a substantially undoped channel, the screening region including a dopant concentration of no less than 1×

10¹⁸ dopant atoms/cm³ with dopants of a conductivity type opposite to that of a source and drain of the DDC transistor.

14. A method, comprising:

determining an offset voltage of an operational amplifier (op amp) having a positive (+) input and a negative (−

) input;

if the offset voltage is greater than a limit, making a change to at least a body bias voltage of a first transistor but not making the same change to a body bias voltage of a second transistor;

determining the offset voltage of the op amp after the change to the body bias voltage;

if the offset voltage is within the limit, using the body bias voltage as an operating body bias voltage for the op amp, and if the offset voltage remains greater than the limit, making another change to the body bias voltage of the first or second transistor;

wherein

the first transistor is coupled to one input of the op amp and the second transistor is coupled to the other input of the op amp.

15. The method of claim 14, wherein:

the first transistor is a first input transistor of a differential pair having a gate coupled to one of the op amp inputs, and

the second transistor is a second input transistor of the differential pair having a gate coupled to the other of the op amp inputs.

16. The method of claim 14, wherein:

the first transistor is a load transistor coupled to a first transistor of a differential pair having a gate coupled to one of the op amp inputs.

17. The method of claim 14, wherein:

making a change to at least the body bias voltage of a first transistor includes applying a combination of body biases to a plurality of transistors; and

making another change to the body bias voltage of the first or second transistor includes applying another, different combination of body biases to the plurality of transistors.

18. The method of claim 14, further including:

determining a polarity of the offset voltage of the op amp;

if the offset voltage is greater than a first limit and positive, increasing a reverse body bias to the first or second transistor coupled to the (+) input of the op amp; and

if the offset voltage magnitude is greater than a second limit and negative, increasing a reverse body bias to the first or second transistor coupled to the (−

) input of the op amp.

19. The method of claim 18, further including:

if the offset voltage is greater than the first limit and positive, and a maximum reverse body bias has been reached for the first or second transistor coupled to the (+) input, increasing a forward body bias to the first or second transistor coupled to the (−

) input; and

if the offset voltage magnitude is greater than the second limit and negative, and a maximum reverse body bias has been reached for the first or second transistor coupled to the (−

) input, increasing a forward body bias to the first or second transistor coupled to the (+) input.

20. The method of claim 14, wherein:

at least the first transistor comprises a deeply depleted channel (DDC) transistor having a screening region formed below a substantially undoped channel, the screening region including

a dopant concentration of no less than 1×

10¹⁸ dopant atoms/cm³ with dopants of a conductivity type opposite to that of a source and drain of the DDC transistor.