Slew based process and bias monitors and related methods
First Claim
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1. An integrated circuit, comprising:
- at least one slew generator circuit comprising at least one body biasable reference transistor, the slew generator circuit configured to generate at least a first signal having a slew rate that varies according to characteristics of the reference transistor;
a pulse generator circuit configured to generate a pulse signal having a first pulse with a duration corresponding to the slew rate of the first signal;
a counter configured to generate a count value corresponding to the duration of the first pulse;
a pulse extender circuit coupled to receive the pulse signal and configured to generate an extended pulse signal with an extended pulse;
whereinthe duration of the extended pulse is proportional to the duration of the first pulse;
the at least one slew generator circuit includes an n-channel reference transistor and a p-channel reference transistor, each of the n-channel reference transistor and the p-channel transistor having a first threshold voltage setting; and
the integrated circuit includes other circuits that include transistors fabricated with the same process as the n-channel and p-channel reference transistors, the other circuits having transistors wherein at least some transistors have a second threshold voltage setting.
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Abstract
An integrated circuit can include at least one slew generator circuit comprising at least one body biasable reference transistor, the slew generator circuit configured to generate at least a first signal having a slew rate that varies according to characteristics of the reference transistor; a pulse generator circuit configured to generate a pulse signal having a first pulse with a duration corresponding to the slew rate of the first signal; and a counter configured to generate a count value corresponding to a duration of the first pulse.
509 Citations
13 Claims
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1. An integrated circuit, comprising:
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at least one slew generator circuit comprising at least one body biasable reference transistor, the slew generator circuit configured to generate at least a first signal having a slew rate that varies according to characteristics of the reference transistor; a pulse generator circuit configured to generate a pulse signal having a first pulse with a duration corresponding to the slew rate of the first signal; a counter configured to generate a count value corresponding to the duration of the first pulse; a pulse extender circuit coupled to receive the pulse signal and configured to generate an extended pulse signal with an extended pulse;
whereinthe duration of the extended pulse is proportional to the duration of the first pulse; the at least one slew generator circuit includes an n-channel reference transistor and a p-channel reference transistor, each of the n-channel reference transistor and the p-channel transistor having a first threshold voltage setting; and the integrated circuit includes other circuits that include transistors fabricated with the same process as the n-channel and p-channel reference transistors, the other circuits having transistors wherein at least some transistors have a second threshold voltage setting. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. An integrated circuit, comprising:
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at least one slew generator circuit comprising at least one reference transistor, the slew generator circuit configured to generate at least a first slew signal having a slew rate that varies according to characteristics of the reference transistor; a pulse generator circuit coupled to receive the first slew signal and configured to drive a pulse signal to a first value when a level of the first slew signal is within first and second limits, and configured to drive the pulse signal to a second value when the level of the first slew signal is outside of the first and second limits; a counter configured to generate a count value corresponding to a duration of the pulse signal at the first value; a digital pulse extender circuit coupled to receive the pulse signal and configured to generate an extended pulse signal with an extended pulse, the duration of the extended pulse being proportional to the duration of the first pulse being at the first value; and at least one body bias control circuit configured to generate a body bias voltage for at least some portions of the integrated circuit in response to the duration of the extended pulse. - View Dependent Claims (10, 11, 12)
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13. An integrated circuit, comprising:
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at least one slew generator circuit comprising at least one body biasable reference transistor, the slew generator circuit configured to generate at least a first signal having a slew rate that varies according to characteristics of the reference transistor; a pulse generator circuit configured to generate a pulse signal having a first pulse with a duration corresponding to the slew rate of the first signal; a counter configured to generate a count value corresponding to a duration of the first pulse; a pulse extender circuit coupled to receive the pulse signal and configured to generate an extended pulse signal with an extended pulse; wherein the duration of the extended pulse is proportional to the duration of the first pulse; and wherein the pulse extender receives an input pulse signal at a first pulse, and generates an extended pulse signal as a digital multiplier of the first pulse, the pulse extender further including a frequency divider.
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Specification