Phase-locked loop (PLL)

• US 9,319,053 B2
• Filed: 07/18/2014
• Issued: 04/19/2016
• Est. Priority Date: 07/18/2014
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Kuo, Feng Wei, Yen, Kuang-Kai, Chen, Huan-Neng, Hsiung, Lee Tsung, Jou, Chewn-Pu, Staszewski, Robert Bogdan
• Primary Examiner(s): Puentes, Daniel
• Application Number:
  US14/334,748
• Publication Number:
  US 20160020776A1
• Time in Patent Office: 641 Days
• US Class Current: 1/1
• CPC Class Codes: H03L 2207/50 All digital phase-locked loop
• CPC Class Codes: H03L 7/093 using special filtering or amplification characteristics in the loop H03L7/087 - H03L7/091 take precedence
• CPC Class Codes: H03L 7/0991 the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider H03L7/0995 takes precedence; fixed oscillators with means for selecting among various phases H03L7/0814

Abstract

A phase-locked loop (PLL) is provided. The PLL comprises a dithering circuit that is configured to receive a second tuning signal, and dither the second tuning signal to generate a dither signal to decrease a magnitude of a spur of the PLL. The dither signal is used by a digitally controlled oscillator (DCO) to generate an output signal of the PLL. Operation of the dithering circuit is controlled using a spur-cancel control circuit. The spur-cancel control circuit receives a frequency command word (FCW) signal and determines a value of an enable signal based on the FCW signal. In some embodiments, the dithering circuit dithers the second tuning signal based on the enable signal.

Claims

1. A phase-locked loop (PLL), comprising:

a dithering circuit configured to;

receive a first tuning signal; and

dither the first tuning signal to generate a dither signal;

a tuning circuit comprising an adder configured to generate a digitally controlled oscillator (DCO) input signal based upon a combination of the dither signal and a second tuning signal; and

a DCO configured to;

receive the DCO input signal generated based on the dither signal and the second tuning signal; and

generate an output signal having an output frequency based on the DCO input signal.

2. The PLL of claim 1, comprising a phase error circuit configured to:

receive a reference phase signal representing a reference phase;

receive a first output phase signal representing a fractional part of an output phase of the output signal;

receive a second output phase signal representing an integer part of the output phase; and

output a phase error signal based on at least one of the reference phase signal, the first output phase signal or the second output phase signal.

3. The PLL of claim 2, the phase error circuit comprising a subtractor configured to subtract the fractional part of the output phase and the integer part of the output phase from the reference phase to generate the phase error signal.

4. A phase-locked loop (PLL), comprising:

a spur-cancel control circuit comprising;

a bit selector configured to;

receive a frequency command word (FCW) signal; and

generate a modified FCW signal representing a fractional part of a FCW represented by the FCW signal; and

a comparator configured to generate an enable signal based on the modified FCW signal;

a dithering circuit configured to;

receive a first tuning signal and the enable signal; and

dither the first tuning signal based on the enable signal to generate a dither signal; and

a digitally controlled oscillator (DCO) configured to;

receive a DCO input signal generated based on at least one of the dither signal or a second tuning signal; and

generate an output signal having an output frequency based on the DCO input signal.

5. The PLL of claim 4, the dithering circuit configured to stop the dithering when the enable signal has a first value.

6. The PLL of claim 4, the dithering circuit configured to start the dithering when the enable signal has a second value.

7. The PLL of claim 4, the spur-cancel control circuit comprising at least one of a clock adjuster or a multiplexer.

8. The PLL of claim 4, the comparator configured to:

receive the modified FCW signal; and

generate the enable signal such that the enable signal has a first value when a fractional part of the FCW is within a first range and the enable signal has a second value when the fractional part of the FCW is outside the first range.

9. The PLL of claim 4, comprising a clock adjuster configured to:

receive an initial clock signal having an initial frequency; and

modify the initial clock signal to a modified clock signal having a modified frequency.

10. The PLL of claim 9, the modified frequency corresponding to the initial frequency divided by a specified divisor.

11. The PLL of claim 10, the specified divisor changeable from a first specified divisor to a second specified divisor.

12. The PLL of claim 9, comprising a multiplexer configured to:

receive at least one of the enable signal, the modified clock signal or the initial clock signal; and

generate a second modified clock signal having a second modified frequency that corresponds to the modified frequency when the enable signal has a first value and having the initial frequency when the enable signal has a second value.

13. The PLL of claim 4, the dithering circuit comprising at least one of one or more flip-flops or one or more adders.

14. A phase-locked loop (PLL), comprising:

a phase error circuit comprising a subtractor and configured to;

receive a reference phase signal representing a reference phase;

receive a first output phase signal representing a fractional part of an output phase of an output signal;

receive a second output phase signal representing an integer part of the output phase; and

subtract the fractional part of the output phase and the integer part of the output phase from the reference phase to generate a phase error signal;

a dithering circuit configured to;

receive a first tuning signal generated based on the phase error signal; and

dither the first tuning signal to generate a dither signal; and

a digitally controlled oscillator (DCO) configured to;

receive a DCO input signal generated based on at least one of the dither signal or a second tuning signal; and

generate the output signal having an output frequency based on the DCO input signal.

15. The PLL of claim 14, comprising:

a tuning circuit comprising an adder configured to generate the DCO input signal based upon a combination of the dither signal and the second tuning signal.

16. A phase-locked loop (PLL), comprising:

a spur-cancel control circuit comprising;

a clock adjuster configured to;

receive an initial clock signal having an initial frequency; and

modify the initial clock signal to a first modified clock signal having a modified frequency;

a multiplexer configured to;

receive an enable signal generated based on a frequency command word (FCW) signal;

receive the first modified clock signal;

receive the initial clock signal; and

generate a second modified clock signal having the modified frequency when the enable signal has a first value and having the initial frequency when the enable signal has a second value;

a dithering circuit configured to;

receive a first tuning signal and the enable signal; and

dither the first tuning signal based on the enable signal to generate a dither signal; and

a digitally controlled oscillator (DCO) configured to;

receive a DCO input signal generated based on at least one of the dither signal or a second tuning signal; and

generate an output signal having an output frequency based on the DCO input signal.

17. The PLL of claim 16, the spur-cancel control circuit comprising:

a bit selector configured to;

receive the FCW signal; and

generate a modified FCW signal representing a fractional part of a FCW represented by the FCW signal; and

a comparator configured to generate the enable signal based on the modified FCW signal.

18. The PLL of claim 17, the comparator configured to:

receive the modified FCW signal; and

generate the enable signal such that the enable signal has a first value when the fractional part of the FCW is within a first range and the enable signal has a second value when the fractional part of the FCW is outside the first range.

19. The PLL of claim 16, the modified frequency corresponding to the initial frequency divided by a specified divisor.

20. The PLL of claim 16, comprising an adder configured to generate the DCO input signal based upon a combination of the dither signal and the second tuning signal.