System and method for a phase detector

• US 9,322,858 B2
• Filed: 02/04/2014
• Issued: 04/26/2016
• Est. Priority Date: 02/04/2014
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Inventors: Solomko, Valentyn
• Primary Examiner(s): Hernandez, William
• Application Number:
  US14/172,675
• Publication Number:
  US 20150219701A1
• Time in Patent Office: 812 Days
• Field of Search: 327/2, 327/3, 327/12
• US Class Current: 1/1
• CPC Class Codes: G01R 25/00 Arrangements for measuring phase angle between a voltage and a current or between voltages or currents
• CPC Class Codes: G01R 25/005 Circuits for comparing several input signals and for indicating the result of this comparison, e.g. equal, different, greater, smaller, or for passing one of the input signals as output signal
• CPC Class Codes: H03D 13/00 Circuits for comparing the phase or frequency of two mutually-independent oscillations measuring phase G01R25/00; phase-discriminators with yes/no output G01R25/005
• CPC Class Codes: H03F 2200/423 Amplifier output adaptation especially for transmission line coupling purposes, e.g. impedance adaptation
• CPC Class Codes: H03F 2200/451 the amplifier being a radio frequency amplifier
• CPC Class Codes: H03F 3/19 with semiconductor devices only
• CPC Class Codes: H04B 1/40 Circuits

Abstract

In accordance with an embodiment, a method of detecting a phase difference between a first signal and a second signal include latching a state of the first signal using the second signal as a clock to produce a first latched signal, latching a state of the second signal using the first signal as a clock to produce a second latched signal summing the first latched signal and the second latched signal to produce an indication of whether the first signal is leading or lagging the second signal.

Claims

1. A method of detecting a phase difference between a first signal and a second signal, the method comprising:

latching, using a first gated latch circuit, a state of the first signal using the second signal as a clock to produce a first latched signal, wherein the first gated latch circuit is transparent when the second signal is asserted, and the first gated latch circuit stores a value of the first signal when the second signal is not asserted;

latching, using a second gated latch circuit, a state of the second signal using the first signal as a clock to produce a second latched signal, wherein the second gated latch circuit is transparent when the first signal is asserted, and the second gated latch circuit stores a value of the second signal when the first signal is not asserted; and

summing the first latched signal and the second latched signal to produce an indication of whether the first signal is leading or lagging the second signal.

2. The method of claim 1, further comprising inverting the second signal at a clock input of the second gated latch circuit.

3. The method of claim 1, further comprising inverting the first latched signal prior to summing the first latched signal and the second latched signal.

4. The method of claim 1, wherein summing comprises low pass filtering the first latched signal and the second latched signal.

5. The method of claim 4, wherein low pass filtering comprises using an RC network.

6. The method of claim 1, further comprising providing the first signal and the second signal from outputs of a directional coupler.

7. The method of claim 6, further comprising detecting an amplitude of the first signal and an amplitude of the second signal.

8. The method of claim 1, wherein the first gated latch circuit and the second gated latch circuit each comprise a differential data input and a differential clock input.

9. A circuit comprising a phase detector circuit, wherein the phase detector circuit comprises:

a first gated latch having a data input coupled to a first input of the phase detector circuit and a clock input coupled to a second input of the phase detector circuit, wherein the first gated latch is transparent when the clock input of the first gated latch is asserted, and the first gated latch stores a value of the data input of the first gated latch when the clock input of the first gated latch is not asserted;

a second gated latch having a data input coupled to the second input of the phase detector circuit and a clock input coupled to the first input of the phase detector circuit, wherein the second gated latch is transparent when the clock input of the second gated latch is asserted, and the second gated latch stores a value of the data input of the second gated latch when the clock input of the second gated latch is not asserted; and

a summing circuit having a first input coupled to an output of the first gated latch and a second input coupled to an output of the second gated latch, wherein an output of the summing circuit indicates whether a signal at the first input of the phase detector circuit is leading or lagging a signal at the second input of the phase detector circuit.

10. The circuit of claim 9, wherein the first input of the summing circuit is coupled to an inverted output of the first gated latch, and the second input of the summing circuit is coupled to a non-inverted output of the second gated latch.

11. The circuit of claim 9, further comprising an inverter circuit coupled between the output of the first gated latch and the first input of the summing circuit.

12. The circuit of claim 9, wherein the clock input of the second gated latch is inverted with respect to the clock input of the first gated latch.

13. The circuit of claim 9, further comprising an inverter circuit coupled between the second input of the phase detector circuit and the clock input of the first gated latch.

14. The circuit of claim 9, wherein the summing circuit comprises:

a first series resistor coupled to an output of the first gated latch;

a second series resistor coupled to an output of the second gated latch; and

a load capacitor coupled to the first series resistor and the second series resistor.

15. The circuit of claim 9, further comprising an RF coupler having a first output coupled to the first input of the phase detector circuit and a second output coupled to the second input of the phase detector circuit.

16. The circuit of claim 15, further comprising a first power detector coupled to the first input of the phase detector circuit, and a second power detector coupled to the second input of the phase detector circuit.

17. A circuit comprising a phase detector circuit, wherein the phase detector circuit comprises:

a first gated latch having a data input coupled to a first input of the phase detector circuit and a clock input coupled to a second input of the phase detector circuit;

a second gated latch having a data input coupled to the second input of the phase detector circuit and a clock input coupled to the first input of the phase detector circuit; and

a summing circuit having a first input coupled to an output of the first gated latch and a second input coupled to an output of the second gated latch, wherein an output of the summing circuit indicates whether a signal at the first input of the phase detector circuit is leading or lagging a signal at the second input of the phase detector circuit, wherein the first gated latch and the second gated latch each comprise a differential data input and a differential clock input.

18. The circuit of claim 17, wherein the first gated latch and the second gated latch each comprise:

a first differential pair of transistors having control nodes coupled to the differential clock input;

a second differential pair of transistors coupled to a first output of the first differential pair of transistors, the second differential pair of transistors having control nodes coupled to the differential data input; and

a third differential pair of transistors coupled to a second output of the first differential pair of transistors, wherein a control node of a first transistor of the third differential pair of transistors is coupled to an output node of a second transistor of the third differential pair of transistors, and a control node of the second transistor of the third differential pair of transistors is coupled to an output node of the first transistor of the third differential pair of transistors.

19. The circuit of claim 18, wherein,

the first differential pair of transistors comprises a first differential pair of MOS transistors;

the second differential pair of transistors comprises a second differential pair of MOS transistors; and

the third differential pair of transistors comprises a third differential pair of MOS transistors.

20. The circuit of claim 17, wherein:

the first gated latch and the second gated latch each further comprise a differential output; and

the summing circuit comprises

a first resistor coupled between a first terminal of the differential output of the first gated latch and a first output of the summing circuit,

a second resistor coupled between a second terminal of the differential output of the first gated latch and a second output of the summing circuit,

a third resistor coupled between a first terminal of the differential output of the second gated latch and the second output of the summing circuit, and

a fourth resistor coupled between a second terminal of the differential output of the second gated latch and the first output of the summing circuit.

21. The circuit of claim 20, wherein the summing circuit further comprises:

a filter capacitor coupled between the first output of the summing circuit and the second output of the summing circuit.

22. The circuit of claim 20, wherein the summing circuit further comprises:

a first capacitor coupled between the first output of the summing circuit and a reference node; and

a second capacitor coupled between the second output of the summing circuit and the reference node.

23. A phase detector comprising:

a plurality of cascaded RF stages, each of the plurality of cascaded RF stages having a first RF amplifier and a second RF amplifier, wherein first RF amplifiers are cascaded with first RF amplifiers of successive RF stages and second RF amplifiers are cascaded with second RF amplifiers of successive RF stages;

a first latch having a first input coupled to an output of a first RF amplifier of a first RF stage, and a second input coupled to an output of a second RF amplifier of the first RF stage;

a second latch having a first input coupled to an output of a second RF amplifier of a second RF stage, and a second input coupled to an output of a first RF amplifier of the second RF stage; and

a summing circuit having inputs coupled to outputs of the first latch and the second latch.

24. The phase detector of claim 23, wherein:

the first input of the first latch is a data input and the second input of the first latch is a clock input; and

the first input of the second latch is a data input and the second input of the second latch is a clock input.

25. The phase detector of claim 23, wherein the first latch is a gated latch and the second latch is a gated latch.