Dynamic self-correcting power management for solid state drive

• US 9,323,304 B2
• Filed: 12/18/2013
• Issued: 04/26/2016
• Est. Priority Date: 12/18/2013
• Status: Active Grant

• Current Assignee: NGD Systems, Inc.
• Original Assignee: NxGn Data, Inc.
• Inventors: Salessi, Nader, Alcantara, Joao
• Primary Examiner(s): Choudhury, Zahid
• Application Number:
  US14/133,159
• Publication Number:
  US 20150169021A1
• Time in Patent Office: 860 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 1/266 Arrangements to supply power to external peripherals either directly from the computer or under computer control, e.g. supply of power through the communication port, computer controlled power-strips
• CPC Class Codes: G06F 1/3268 Power saving in hard disk drive
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: G11C 2029/0409 Online test
• CPC Class Codes: G11C 29/021 in voltage or current generators
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 5/14 Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A system and method for operating a solid state drive (SSD) within power limitations while maintaining SSD performance. In one embodiment a power management integrated circuit (PMIC) is used to measure power consumption, and a built-in self-test (BIST) procedure is used to exercise the storage device, and to calibrate the power consumed by various SSD operations. The results are stored in a power consumption cost table. In one embodiment, a procedure to dynamically adjust the power consumption cost table is employed. A power credit allocation scheme is used, along with the power consumption cost table, to track and limit the power consumed by the SSD in operation.

Claims

1. A system for power management in a solid state drive (SSD) comprising a flash memory, the system comprising:

a controller; and

a power management integrated circuit (PMIC),

the controller configured to receive commands, each command corresponding to a requested read operation, a requested write operation, or a requested erase operation to be dispatched to the flash memory,

the controller configured to place each command in a command queue, and to dispatch each command from the command queue to the flash memory, according to an algorithm, so as to maintain a power consumption of the solid state drive below a maximum acceptable power consumption value, the algorithm employing a power consumption cost table,

the controller configured to dynamically adjust the power consumption cost table based on information received from the PMIC,

wherein the algorithm comprises;

forming a pool containing a quantity of credits proportional to the maximum acceptable power consumption value;

removing a first quantity of credits from the pool for each write operation conducted, at the beginning of the write operation, and replacing the first quantity of credits at the completion of the write operation, the first quantity of credits being proportional to a mean power consumption of a write operation;

removing a second quantity of credits from the pool for each read operation conducted, at the beginning of the read operation, and replacing the second quantity of credits at the completion of the read operation, the second quantity of credits being proportional to a mean power consumption of a read operation;

removing a third quantity of credits from the pool for each erase operation conducted, at the beginning of the erase operation, and replacing the third quantity of credits at the completion of the erase operation, the third quantity of credits being proportional to a mean power consumption of an erase operation, the mean power consumption of the write operation, the mean power consumption of the read operation, and the mean power consumption of the erase operation being determined from the power consumption cost table; and

delaying a command in the command queue when there are insufficient credits in the pool for the command.

2. The system of claim 1, wherein the controller is configured to dynamically adjust the power consumption cost table by:

performing a built-in-self-test (BIST) procedure comprising;

a plurality of test read operations;

a plurality of test write operations; and

a plurality of test erase operations; and

measuring the power consumed by the performing of the plurality of test read operations, the plurality of test write operations, and the plurality of test erase operations.

3. The system of claim 1, wherein the controller is configured to dynamically adjust the power consumption cost table prior to initial operation of the SSD.

4. The system of claim 1, wherein the controller is configured to dynamically adjust the power consumption cost table by correlating, during operation of the solid state drive, power consumption data from the PMIC with a frequency to simultaneously perform read operations, write operations, and erase operations.

5. The system of claim 4, wherein the controller is configured to dynamically adjust the power consumption cost table only when the power consumption of the solid state drive exceeds a threshold fraction of the maximum acceptable power consumption value.

6. The system of claim 5, wherein the threshold fraction is 50%.

7. The system of claim 1, wherein the controller comprises a flash manager.

8. The system of claim 1, wherein the controller comprises a central processing unit (CPU).

9. A method for operating a solid state drive comprising a controller, a flash memory, and a power management integrated circuit (PMIC), the method comprising:

receiving commands, each command corresponding to a requested read operation, a requested write operation, or a requested erase operation to be executed in the flash memory;

placing each command in a command queue;

dispatching each command from the command queue to the flash memory, according to an algorithm, so as to maintain a power consumption of the solid state drive below a maximum acceptable power consumption value, the algorithm employing a power consumption cost table;

dynamically adjusting, by the controller, the power consumption cost table based on information received from the PMIC;

forming a pool containing a quantity of credits proportional to the maximum acceptable power consumption value;

removing a first quantity of credits from the pool for each write operation conducted, at the beginning of the write operation, and replacing the first quantity of credits at the completion of the write operation, the first quantity of credits being proportional to a mean power consumption of a write operation;

removing a second quantity of credits from the pool for each read operation conducted, at the beginning of the read operation, and replacing the second quantity of credits at the completion of the read operation, the second quantity of credits being proportional to a mean power consumption of a read operation;

removing a third quantity of credits from the pool for each erase operation conducted, at the beginning of the erase operation, and replacing the third quantity of credits at the completion of the erase operation, the third quantity of credits being proportional to a mean power consumption of an erase operation, the mean power consumption of the write operation, the mean power consumption of the read operation, and the mean power consumption of the erase operation being determined from the power consumption cost table; and

delaying a command in the command queue when there are insufficient credits in the pool for the command.

10. The method of claim 9, comprising dynamically adjusting, by the controller, the power consumption cost table prior to initial operation of the solid state drive.

11. The method of claim 9, wherein the dynamically adjusting, by the controller, of the power consumption cost table comprises:

performing, under the control of the controller executing a built-in-self-test (BIST) procedure, a plurality of test read operations, a plurality of test write operations, and a plurality of test erase operations; and

measuring the power consumed by the performing of the plurality of test read operations, the plurality of test write operations, and the plurality of test erase operations.

12. The method of claim 11, wherein the measuring of the power consumed by the performing of the plurality of test read operations, the plurality of test write operations, and the plurality of test erase operations comprises measuring, by a power management integrated circuit (PMIC), the power consumed by the performing of the plurality of test read operations, the plurality of test write operations, and the plurality of test erase operations.