Random number generator functions in memory

• US 9,323,499 B2
• Filed: 12/21/2012
• Issued: 04/26/2016
• Est. Priority Date: 11/15/2012
• Status: Active Grant

• Current Assignee: Elwha LLC (Intellectual Ventures LLC)
• Original Assignee: Elwha LLC (Intellectual Ventures LLC)
• Inventors: Hyde, Roderick A., Pasch, Nicholas F., Tegreene, Clarence T.
• Primary Examiner(s): Malzahn, David H
• Application Number:
  US13/725,788
• Publication Number:
  US 20140136583A1
• Time in Patent Office: 1,222 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G06F 7/588 Random number generators, i.e. based on natural stochastic processes

Abstract

A memory device includes but is not limited to a substrate, a non-volatile memory array integrated on the substrate, and random number generator logic integrated with the non-volatile memory array on the substrate. The random number generator logic is operable to perform at least one random number generator function in association with the non-volatile memory array. In addition to the foregoing, other aspects are described in the claims, drawings, and text forming a part of the present disclosure.

Claims

1. A memory device comprising:

a substrate;

a non-volatile memory array integrated on the substrate, wherein the non-volatile memory array is partitioned into a plurality of memory blocks; and

random number generator logic integrated with the non-volatile memory array on the substrate, the random number generator logic operable to perform at least one random number generator function in association with the non-volatile memory array partitioned into a plurality of logic blocks spatially distributed over the non-volatile memory array wherein one or more of the plurality of logic blocks are associated with one or more of the plurality of memory blocks.

2. The memory device according to claim 1 wherein:

the random number generator logic operable to perform at least one random number generator function in association with the non-volatile memory array is operable to supply a source of entropy for generating random numbers.

3. The memory device according to claim 1 wherein:

the non-volatile memory array includes a plurality of non-volatile memory segments characterized by a respective plurality of non-volatile memory types; and

the random number generator logic operable to perform at least one random number generator function in association with the non-volatile memory array is operable to use the plurality of non-volatile memory segments characterized by the respective plurality of non-volatile memory types to supply a source of entropy for generating random numbers.

4. The memory device according to claim 1 further comprising:

at least one sensor operable to detect at least one operating condition, wherein;

the random number generator logic operable to perform at least one random number generator function in association with the non-volatile memory array is operable to use the at least one operating condition to supply a source of entropy for generating random numbers.

5. The memory device according to claim 1 further comprising:

at least one sensor operable to detect at least one operating condition, wherein;

the random number generator logic operable to perform at least one random number generator function in association with the non-volatile memory array is operable to monitor the at least one operating condition, monitor memory accesses, analyze the monitored at least one operating condition and memory accesses, and determine a source of entropy for generating random numbers based on the analysis of the monitored at least one operating condition and memory accesses.

6. The memory device according to claim 1 wherein:

the non-volatile memory array includes at least in part lossy memory; and

the random number generator logic operable to perform at least one random number generator function in association with the non-volatile memory array is operable use the lossy memory to supply a source of entropy for generating random numbers.

7. The memory device according to claim 1 wherein:

the random number generator logic operable to perform at least one random number generator function in association with the non-volatile memory array is operable to access a time signal and determine a source of entropy for generating random numbers based on the time signal.

8. The memory device according to claim 1 wherein:

the random number generator logic operable to perform at least one random number generator function in association with the non-volatile memory array is operable to access a time signal, monitor memory accesses referenced by the time signal, and determine a source of entropy for generating random numbers based on the time signal and the memory accesses referenced by the time signal.

9. The memory device according to claim 1 wherein:

the random number generator logic operable to perform at least one random number generator function in association with the non-volatile memory array is operable to monitor phenomena detectable at the memory device and determine a source of entropy for generating random numbers based on the monitored phenomena.

10. The memory device according to claim 1 wherein:

the random number generator logic operable to perform at least one random number generator function in association with the non-volatile memory array is operable to accumulate and communicate information about phenomena associated with use of the memory device and determine a source of entropy for generating random numbers based on the monitored phenomena.

11. The memory device according to claim 1 wherein:

the random number generator logic operable to perform at least one random number generator function in association with the non-volatile memory array is operable to accumulate and communicate information about phenomena associated with at least one entity in association with the memory device and determine a source of entropy for generating random numbers based on the monitored phenomena.

12. The memory device according to claim 1 wherein:

the random number generator logic operable to perform at least one random number generator function in association with the non-volatile memory array is operable to supply a seed for a pseudo-random number generator in association with the non-volatile memory array.

13. The memory device according to claim 1 wherein:

the non-volatile memory array includes a plurality of non-volatile memory segments characterized by a respective plurality of non-volatile memory types; and

the random number generator logic operable to perform at least one random number generator function in association with the non-volatile memory array is operable to supply a seed for a pseudo-random number generator in association with the plurality of non-volatile memory segments characterized by the respective plurality of non-volatile memory types.

14. The memory device according to claim 1 further comprising:

encryption logic integrated with the non-volatile memory array on the substrate, the encryption logic operable to perform at least one encryption/decryption function associated with the non-volatile memory array.

15. The memory device according to claim 1 further comprising:

encryption logic integrated with the non-volatile memory array on the substrate, the encryption logic operable to perform at least one encryption/decryption function associated with the non-volatile memory array that increases throughput of encryption-type operations in combination with a device external to the memory device.

16. The memory device according to claim 1 further comprising:

encryption logic integrated with the non-volatile memory array on the substrate, the encryption logic operable to perform at least one encryption/decryption function associated with the non-volatile memory array that secures at least one encryption key from access by a device external to the memory device.

17. The memory device according to claim 1 further comprising:

hash logic integrated with the non-volatile memory array on the substrate, the hash logic operable to perform a hash function using randomness supplied by the random number generator logic.

18. The memory device according to claim 1 further comprising:

searching logic integrated with the non-volatile memory array on the substrate, the searching logic operable to perform amortized searching using randomness supplied by the random number generator logic.

19. The memory device according to claim 1 further comprising:

sorting logic integrated with the non-volatile memory array on the substrate, the sorting logic operable to perform data sorting using randomness supplied by the random number generator logic.

20. The memory device according to claim 1 further comprising:

sorting logic integrated with the non-volatile memory array on the substrate, the sorting logic operable to monitor a history and pattern of memory accesses and perform sorting during system idle.

21. The memory device according to claim 1 further comprising:

a bus integrated with the encryption logic and the non-volatile memory array on the substrate, the bus operable to transmit encrypted information between the memory device and a device external to the memory device.

22. The memory device according to claim 1 wherein:

the random number generator logic operable to perform at least one random number generator function in association with the non-volatile memory array is operable to perform at least one random number generator function independently of signals external to the memory device.

23. The memory device according to claim 1 wherein:

the random number generator logic operable to perform at least one random number generator function in association with the non-volatile memory array is configured with functionality selectively distributed across the non-volatile memory array.

24. The memory device according to claim 1 wherein:

the random number generator logic operable to perform at least one random number generator function in association with the non-volatile memory array is operable to receive a report on at least one operating condition of system performance at system bootstrap loading and allocate functionality of one or more of the plurality of logic blocks with one or more of the plurality of memory blocks based on the report.

25. The memory device according to claim 1 further comprising:

optical silicon operable to communicate optically, independently of a bus coupled to the memory device wherein;

the random number generator logic operable to perform at least one random number generator function in association with the non-volatile memory array is operable to receive information from the optical silicon and determine a source of entropy for generating random numbers based on the received information.

26. The memory device according to claim 1 wherein:

the non-volatile memory array partitioned into a plurality of memory blocks includes at least one memory technology of flash, embedded flash, read-only memory (ROM), electrical fuse (one-time programmable), CMOS floating gate (multiple time programmable), CMOS floating gate (one-time programmable), anti-fuse (one-time programmable), phase-change memory (PCRAM), spin-torque transfer (STT) magneto-resistive RAM (M-RAM), or ferroelectric RAM (FRAM).

27. A memory device comprising:

a substrate;

a non-volatile memory array integrated on the substrate, wherein the non-volatile memory array is partitioned into a plurality of memory blocks; and

random number generator logic integrated with the non-volatile memory array on the substrate, the random number generator logic operable to perform at least one random number generator function in association with the non-volatile memory array including monitoring memory accesses, determining statistics on type and number of instructions of the monitored memory accesses, and allocating at least one random number generator function among the plurality of memory blocks based on the determined statistics.

28. A memory device comprising:

a substrate;

a non-volatile memory array integrated on the substrate, wherein the non-volatile memory array is partitioned into a plurality of memory blocks characterized by a plurality of different operating characteristics; and

random number generator logic integrated with the non-volatile memory array on the substrate, the random number generator logic operable to perform at least one random number generator function in association with the non-volatile memory array partitioned into a plurality of logic blocks spatially distributed over the non-volatile memory array wherein one or more of the plurality of logic blocks are associated with one or more of the plurality of memory blocks at least partly based on the operating characteristics of the plurality of memory blocks.

29. The memory device according to claim 28 wherein:

the random number generator logic operable to perform at least one random number generator function in association with the non-volatile memory array is operable to monitor operating characteristics of the memory device, analyze the monitored operating characteristics, and allocate at least one random number generator function among the plurality of memory blocks based on the analysis.

30. The memory device according to claim 28 wherein:

the random number generator logic operable to perform at least one random number generator function in association with the non-volatile memory array is operable to monitor operating characteristics of the memory device, analyze the monitored operating characteristics, and determine a source of entropy for generating random numbers based on the analysis of the monitored operating characteristics.

31. A memory device comprising:

a substrate;

a non-volatile memory array integrated on the substrate, wherein the non-volatile memory array includes a plurality of memory blocks; and

random number generator logic integrated with the non-volatile memory array on the substrate, the random number generator logic operable to perform at least one random number generator function in association with the non-volatile memory array including monitoring writes to the plurality of memory blocks of the non-volatile memory array and allocating at least one random number generator function among the plurality of memory blocks based on results of the monitoring.

32. A method of manufacturing a memory device comprising:

forming a non-volatile memory array on a substrate;

partitioning the non-volatile memory array into a plurality of memory blocks;

integrating random number generator logic in combination with the non-volatile memory array on the substrate, the random number generator logic operable to perform at least one random number generator function in association with the non-volatile memory array; and

partitioning the random number generator logic into a plurality of logic blocks spatially distributed over the non-volatile memory array wherein one or more of the plurality of logic blocks are associated with one or more of the plurality of memory blocks.

33. The method of manufacturing the memory device according to claim 32 further comprising:

forming a plurality of non-volatile memory segments characterized by a respective plurality of non-volatile memory types in the non-volatile memory array; and

integrating the random number generator logic in combination with the non-volatile memory array on the substrate that is operable to use a plurality of non-volatile memory segments characterized by a respective plurality of non-volatile memory types to supply a source of entropy for generating random numbers.

34. The method of manufacturing the memory device according to claim 32 further comprising:

forming a plurality of non-volatile memory segments characterized by a respective plurality of non-volatile memory types in the non-volatile memory array; and

integrating the random number generator logic in combination with the non-volatile memory array on the substrate that is operable to supply a seed for a pseudo-random number generator in association with a plurality of non-volatile memory segments characterized by a respective plurality of non-volatile memory types.

35. The method of manufacturing the memory device according to claim 32 further comprising:

coupling at least one sensor operable to detect at least one operating condition to the memory device; and

integrating the random number generator logic in combination with the non-volatile memory array on the substrate that is operable use the at least one operating condition to supply a source of entropy for generating random numbers.

36. An information processing system comprising:

means for storing information including random number generator logic integrated in combination with a non-volatile memory array on a substrate;

means for partitioning the non-volatile memory array into a plurality of memory blocks;

means for performing at least one random number generator function in association with the non-volatile memory array; and

means for partitioning the random number generator logic into a plurality of logic blocks spatially distributed over the non-volatile memory array wherein one or more of the plurality of logic blocks are associated with one or more of the plurality of memory blocks.