Data recovery once ECC fails to correct the data

• US 9,323,607 B2
• Filed: 05/09/2014
• Issued: 04/26/2016
• Est. Priority Date: 04/29/2014
• Status: Active Grant

• Current Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Original Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Inventors: Cai, Yu, Wu, Yunxiang, Haratsch, Erich F.
• Primary Examiner(s): Torres, Joseph D
• Application Number:
  US14/273,920
• Publication Number:
  US 20150309872A1
• Time in Patent Office: 718 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 11/1024 Identification of the type of error
• CPC Class Codes: G06F 11/1064 in cache or content addressable memories
• CPC Class Codes: G06F 11/1076 Parity data used in redundant arrays of independent storages, e.g. in RAID systems
• CPC Class Codes: G11C 16/3436 Arrangements for verifying correct programming or erasure
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 2029/0409 Online test
• CPC Class Codes: G11C 29/04 Detection or location of defective memory elements , e.g. cell constructio details, timing of test signals
• CPC Class Codes: G11C 29/42 using error correcting codes [ECC] or parity check
• CPC Class Codes: G11C 29/4401 for self repair
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents
• CPC Class Codes: G11C 29/72 with optimized replacement algorithms

Abstract

An apparatus comprising a memory and a controller. The memory is configured to process a plurality of read/write operations. The memory comprises a plurality of memory modules each having a size less than a total size of the memory. The controller is configured to salvage data stored in a failed page of the memory determined to exceed a maximum number of errors. The controller copies raw data stored in the failed page. The controller identifies locations of a first type of data cells that fail erase identification. The controller identifies locations of a second type of data cells that have program errors. The controller flips data values in the raw data at the locations of the first type of data cells and the locations of the second type of data cells. The controller is configured to perform error correcting code decoding on the raw data having flipped data values. The controller salvages data stored in the failed page.

Claims

1. An apparatus comprising:

a memory configured to store data, the memory comprising a plurality of memory modules each having a size less than a total size of the memory; and

a controller configured to (A) process a plurality of read/write operations and (B) salvage data stored in a failed page of the memory determined to exceed a maximum number of errors, wherein the controller (i) copies raw data stored in the failed page, (ii) identifies locations of a first type of data cells that fails erase identification, (iii) identifies locations of a second type of data cells that has program errors, (iv) flips data values in the raw data at the locations of the first type of data cells and the locations of the second type of data cells, (v) performs error correcting code decoding on the raw data having flipped data values, and (vi) salvages data stored in the failed page.

2. The apparatus according to claim 1, wherein the first type of data cells and the second type of data cells have permanent cell damage.

3. The apparatus according to claim 2, wherein the permanent cell damage is caused by program/erase cycling.

4. The apparatus according to claim 1, wherein the maximum number of errors is a value above an error correcting capability threshold of the error correcting code.

5. The apparatus according to claim 1, wherein a number of errors in the data after salvaging the data is a value below an error correcting capability threshold of the error correcting code.

6. The apparatus according to claim 1, wherein the flipped data increases a probability that the data stored in the failed page of the memory will be salvaged.

7. The apparatus according to claim 1, wherein the identification of the locations of the first type of data cells and the identification of the locations of the second type of data cells excludes data cells in the failed page of the memory that have transient errors.

8. The apparatus according to claim 1, wherein a block of the memory containing the failed page is marked as invalid after the data in the failed page is salvaged.

9. The apparatus according to claim 1, wherein a refresh frequency of a block of the memory containing the failed page is increased after the data in the failed page is salvaged.

10. The apparatus according to claim 1, wherein a block of the memory containing the failed page is marked as invalid if the data in the failed page cannot be salvaged.

11. The apparatus according to claim 1, wherein the controller is further configured to track a location of memory blocks of the memory that are known to be reliable.

12. The apparatus according to claim 11, wherein the raw data stored in the failed page is copied to the memory blocks of the memory that are known to be reliable.

13. The apparatus according to claim 12, wherein new parity bits are calculated to protect the raw data copied to the memory blocks of the memory that are known to be reliable.

14. The apparatus according to claim 1, wherein the raw data stored in the failed page is copied to (A) buffers in a first mode and (B) cache in a second mode.

15. The apparatus according to claim 1, wherein the errors are correctable errors.

16. The apparatus according to claim 1, wherein other pages stored in a memory block containing the failed page are read and (i) are corrected by error correcting code decoding, and (ii) copied to a known reliable location of the memory if the other pages fail error correcting code decoding.

17. The apparatus according to claim 1, wherein the locations of the first type of data cells are identified by (i) erasing a block of the memory containing the failed page, (ii) reading the failed page, and (iii) recording locations of cells with a read value of logical 0.

18. The apparatus according to claim 1, wherein the locations of the second type of data cells are identified by (i) programming a known data pattern into the failed page, (ii) reading a data pattern from the failed page, (iii) comparing the data pattern read from the failed page with the known data pattern, and (iv) recording locations of cells in the failed page that do not match the known data pattern.

19. An apparatus comprising:

an interface configured to process a plurality of read/write operations to/from a memory; and

a control circuit configured to salvage data stored in a failed page of the memory determined to exceed a maximum number of errors, wherein the control circuit (i) copies raw data stored in the failed page, (ii) identifies locations of a first type of data cells that fails erase identification, (iii) identifies locations of a second type of data cells that has program errors, (iv) flips data values in the raw data at the locations of the first type of data cells and the locations of the second type of data cells, (v) performs error correcting code decoding on the raw data having flipped data values, and (vi) salvages data stored in the failed page.

20. A method for salvaging data in a flash memory, comprising:

copying raw data stored in a failed page of the flash memory;

identifying locations of a first type of data cells, wherein the first type of data cells fails erase identification;

identifying locations of a second type of data cells, wherein the second type of data cells has program errors;

flipping data values in the raw data at the locations of the first type of data cells and the locations of the second type of data cells; and

salvaging data stored in the failed page.