Anti-tamper system based on dual random bits generators for integrated circuits
First Claim
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1. A method comprising:
- generating first and second pseudo-random numbers using first and second pseudo-random number generators (PRNGs) in an electronic mesh block, respectively;
transmitting a first plurality of pseudo-random signals indicating the first pseudo-random number through a first plurality of mesh wires to a mesh buffer;
converting the first plurality of pseudo-random signals into a first plurality of input signals;
comparing the first plurality of input signals with a second plurality of input signals indicating the second pseudo-random number to generate an output signal from the electronic mesh block;
generating a clock tamper detect signal in a clock tamper detector;
setting the clock tamper detect signal to a logic value at a first time; and
setting the clock tamper detect signal to a result of an OR operation at a second time subsequent to the first time,wherein the output signal indicates an occurrence of an unauthorized activity on the electronic mesh block, andwherein converting the first plurality of pseudo-random signals into the first plurality of input signals comprises rearranging and inverting the first plurality of pseudo-random signals to generate a plurality of modified signals using the mesh buffer.
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Abstract
An apparatus includes a mesh block, a first number generator configured to generate a first number, a second number generator configured to generate a second number, and a comparator block configured to compare the first number with the second number and generate an output signal from the mesh block. The output signal indicates an occurrence of an unauthorized activity on the mesh block.
22 Citations
20 Claims
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1. A method comprising:
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generating first and second pseudo-random numbers using first and second pseudo-random number generators (PRNGs) in an electronic mesh block, respectively; transmitting a first plurality of pseudo-random signals indicating the first pseudo-random number through a first plurality of mesh wires to a mesh buffer; converting the first plurality of pseudo-random signals into a first plurality of input signals; comparing the first plurality of input signals with a second plurality of input signals indicating the second pseudo-random number to generate an output signal from the electronic mesh block; generating a clock tamper detect signal in a clock tamper detector; setting the clock tamper detect signal to a logic value at a first time; and setting the clock tamper detect signal to a result of an OR operation at a second time subsequent to the first time, wherein the output signal indicates an occurrence of an unauthorized activity on the electronic mesh block, and wherein converting the first plurality of pseudo-random signals into the first plurality of input signals comprises rearranging and inverting the first plurality of pseudo-random signals to generate a plurality of modified signals using the mesh buffer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 19)
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9. An apparatus comprising:
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an electronic mesh block; a first pseudo-random number generator (PRNG) configured to generate a first pseudo-random number; a second PRNG configured to generate a second pseudo-random number; a first plurality of mesh wires configured to transmit a first plurality of pseudo-random signals indicating the first pseudo-random number; a mesh buffer and an inverting block configured to convert the first plurality of pseudo-random signals into a first plurality of input signals; a comparator configured to compare the first plurality of input signals with a second plurality of input signals indicating the second pseudo-random number and generate an output signal from the electronic mesh block, the output signal indicating an occurrence of an unauthorized activity on the electronic mesh block; and a clock tamper detector to generate a clock tamper detect signal, to set the clock tamper detect signal to a logic value at a first time, and to set the clock tamper detect signal to a result of an OR operation at a second time subsequent to the first time, wherein the first PRNG, the second PRNG, and the comparator are provided in the electronic mesh block, and wherein the mesh buffer includes a plurality of inverters configured to rearrange and invert the first plurality of pseudo-random signals to generate a plurality of modified signals. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16, 17, 18, 20)
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Specification