Selective dual cycle write operation for a self-timed memory

• US 9,324,414 B2
• Filed: 07/24/2013
• Issued: 04/26/2016
• Est. Priority Date: 07/24/2013
• Status: Active Grant

• Current Assignee: STMicroelectronics International N.V. (STMicroelectronics NV)
• Original Assignee: STMicroelectronics International N.V. (STMicroelectronics NV)
• Inventors: Kohli, Nishu, Kumar, Shishir
• Primary Examiner(s): Hoang, Huan
• Assistant Examiner(s): DINH, MINH D
• Application Number:
  US13/949,449
• Publication Number:
  US 20150029795A1
• Time in Patent Office: 1,007 Days
• Field of Search: 365/189.14, 365/189.15, 365/189.16, 365/189.04
• US Class Current: 1/1
• CPC Class Codes: G11C 11/419 Read-write [R-W] circuits
• CPC Class Codes: G11C 7/227 Timing of memory operations based on dummy memory elements or replica circuits

Abstract

A write is performed to a first cell of a memory at a first row and column during a first memory access cycle. A memory access operation is made to a second cell at a second row and column during an immediately following second memory access cycle. If the memory access is a read from the second cell and the second row is the same as the first row, or if the memory access is a write to the second cell and the second row is the same as the first row and the second column is different than the first column, then a simultaneous operation is performed during the second memory access cycle. The simultaneous operation is an access of the second cell (for read or write) and a re-write of data from the first memory access cycle write operation back to the first cell.

Claims

1. A method, comprising:

performing a write operation to a first cell of a memory array at a first row and first column location during a first memory access cycle; and

performing a memory access operation to a second cell of the memory array at a second row and second column location during a second memory access cycle, said second memory access cycle immediately following the first memory access cycle, wherein performing comprises;

determining if the second row is a same row as the first row;

determining if the second column is a different column than the first column; and

if the second row is the same row as the first row and the memory access operation is a read, or if the second row is the same row as the first row, the second column is the different column than the first column and the memory access operation is a write, then;

simultaneously within said second memory access cycle accessing the second cell and re-writing data from the first memory access cycle write operation to the first cell.

2. The method of claim 1, wherein performing the write operation to the first cell further comprises storing the data from the first memory access cycle write operation in a storage element distinct from the first cell of the memory array.

3. The method of claim 2, wherein re-writing data from the first memory access cycle write operation to the first cell comprises writing the data in the storage element to the first cell.

4. The method of claim 1, wherein accessing the second cell comprises reading data from the second cell during the second memory access cycle.

5. The method of claim 1, wherein accessing the second cell comprises writing data to the second cell during the second memory access cycle.

6. The method of claim 1, wherein performing further comprises if the second row is the same row as the first row, the second column is not different from the first column and the memory access operation is a read, then:

simultaneously within said second memory access cycle performing the read and re-writing data from the first memory access cycle write operation to the first cell.

7. A method, comprising:

performing a first write operation to a first cell of a memory array at a first row and first column location during a first memory access cycle; and

performing a second write operation to a second cell of the memory array at a second row and second column location during a second memory access cycle, said second memory access cycle immediately following the first memory access cycle, wherein performing comprises;

determining if the second row is a same row as the first row;

determining if the second column is a different column than the first column; and

if both determinations are positive, then;

simultaneously within said second memory access cycle writing to the second cell and re-writing data from the first memory access cycle first write operation to the first cell.

8. The method of claim 7, wherein performing the write operation to the first cell further comprises storing the data from the first memory access cycle first write operation in a storage element distinct from the first cell of the memory array.

9. The method of claim 8, wherein re-writing data from the first memory access cycle first write operation to the first cell comprises writing the data in the storage element to the first cell.

10. A method, comprising:

performing a write operation to a first cell of a memory array at a first row and first column location during a first memory access cycle; and

performing a read operation from a second cell of the memory array at a second row and second column location during a second memory access cycle, said second memory access cycle immediately following the first memory access cycle, wherein performing comprises;

determining if the second row is a same row as the first row; and

if said determination is positive, then;

simultaneously within said second memory access cycle reading from the second cell and re-writing data from the first memory access cycle write operation to the first cell.

11. The method of claim 10, wherein performing the write operation to the first cell further comprises storing the data from the first memory access cycle write operation in a storage element distinct from the first cell of the memory array.

12. The method of claim 11, wherein re-writing data from the first memory access cycle write operation to the first cell comprises writing the data in the storage element to the first cell.

13. The method of claim 10, wherein performing further comprises:

determining if the second column is a different column than the first column; and

if the second row is the same row as the first row and the second column is not different from the first column, then;

simultaneously within said second memory access cycle performing the read and re-writing data from the first memory access cycle write operation to the first cell.

14. A circuit, comprising:

a memory array including a plurality of memory cells arranged in rows and columns;

a control circuit configured to control read and write access to the memory array, said control circuit operable to;

determine whether a write operation during a first memory access cycle to a first cell and a memory access operation during a second memory access cycle to a second cell share access to a same row and different column of the memory array, said second memory access cycle immediately following the first memory access cycle; and

if there is a same row and the memory access operation is a read, or if there is a same row and different column and the memory access operation is a write, then;

simultaneously within said second memory access cycle access the second cell and re-write data from the first memory access cycle write operation to the first cell.

15. The circuit of claim 14, further comprising a storage element distinct from the first cell of the memory array, said control circuit further operable, when performing the write operation to the first cell, to further store the data from the first memory access cycle write operation in said storage element.

16. The circuit of claim 15, wherein said control circuit is further operable in the re-write of data from the first memory access cycle write operation to the first cell to write data from the storage element to the first cell.

17. The circuit of claim 14, wherein said memory access operation is a read of data from the second cell during the second memory access cycle.

18. The circuit of claim 14, wherein said memory access operation is a write of data to the second cell during the second memory access cycle.

19. The circuit of claim 14, wherein said control circuit is further operable if the second row is the same row as the first row, the second column is not different from the first column and the memory access operation is a read, to simultaneously within said second memory access cycle perform the read and re-write data from the first memory access cycle write operation to the first cell.

20. A circuit, comprising:

a memory array including a plurality of memory cells arranged in rows and columns; and

a control circuit configured to control read and write access to the memory array, said control circuit operable to;

determine whether a first write operation during a first memory access cycle to a first cell and a second write operation during a second memory access cycle to a second cell share access to a same row and different column of the memory array, said second memory access cycle immediately following the first memory access cycle; and

if there is a same row and different column, then;

simultaneously within said second memory access cycle perform the write access operation on the second cell and perform a re-write of the data from the first memory access cycle write operation to the first cell.

21. The circuit of claim 20, further comprising a storage element distinct from the first cell of the memory array, said control circuit further operable, when performing the write operation to the first cell, to further store the data from the first memory access cycle first write operation in said storage element, and further in the re-write of data from the first memory access cycle write operation to the first cell to write data from the storage element to the first cell.

22. A circuit, comprising:

a memory array including a plurality of memory cells arranged in rows and columns; and

a control circuit configured to control read and write access to the memory array, said control circuit operable to;

determine whether a write operation during a first memory access cycle to a first cell and a read access operation during a second memory access cycle to a second cell share access to a same row of the memory array, said second memory access cycle immediately following the first memory access cycle; and

if there is a same row access operation is a read, then;

simultaneously within said second memory access cycle perform the read access operation on the second cell and perform a re-write of the data from the first memory access cycle write operation to the first cell.

23. The circuit of claim 22, further comprising a storage element distinct from the first cell of the memory array, said control circuit further operable, when performing the write operation to the first cell, to further store the data from the first memory access cycle write operation in said storage element, and further in the re-write of data from the first memory access cycle write operation to the first cell to write data from the storage element to the first cell.

24. The circuit of claim 22, wherein said control circuit is further operable to:

determine whether the write operation and read access operation share access to a same column of the memory array if the second row is the same row as the first row and the second column is not different from the first column, to simultaneously within said second memory access cycle perform the read and re-write data from the first memory access cycle write operation to the first cell.