Selective dual cycle write operation for a self-timed memory
First Claim
1. A method, comprising:
- performing a write operation to a first cell of a memory array at a first row and first column location during a first memory access cycle; and
performing a memory access operation to a second cell of the memory array at a second row and second column location during a second memory access cycle, said second memory access cycle immediately following the first memory access cycle, wherein performing comprises;
determining if the second row is a same row as the first row;
determining if the second column is a different column than the first column; and
if the second row is the same row as the first row and the memory access operation is a read, or if the second row is the same row as the first row, the second column is the different column than the first column and the memory access operation is a write, then;
simultaneously within said second memory access cycle accessing the second cell and re-writing data from the first memory access cycle write operation to the first cell.
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Accused Products
Abstract
A write is performed to a first cell of a memory at a first row and column during a first memory access cycle. A memory access operation is made to a second cell at a second row and column during an immediately following second memory access cycle. If the memory access is a read from the second cell and the second row is the same as the first row, or if the memory access is a write to the second cell and the second row is the same as the first row and the second column is different than the first column, then a simultaneous operation is performed during the second memory access cycle. The simultaneous operation is an access of the second cell (for read or write) and a re-write of data from the first memory access cycle write operation back to the first cell.
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Citations
24 Claims
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1. A method, comprising:
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performing a write operation to a first cell of a memory array at a first row and first column location during a first memory access cycle; and performing a memory access operation to a second cell of the memory array at a second row and second column location during a second memory access cycle, said second memory access cycle immediately following the first memory access cycle, wherein performing comprises; determining if the second row is a same row as the first row; determining if the second column is a different column than the first column; and if the second row is the same row as the first row and the memory access operation is a read, or if the second row is the same row as the first row, the second column is the different column than the first column and the memory access operation is a write, then; simultaneously within said second memory access cycle accessing the second cell and re-writing data from the first memory access cycle write operation to the first cell. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A method, comprising:
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performing a first write operation to a first cell of a memory array at a first row and first column location during a first memory access cycle; and performing a second write operation to a second cell of the memory array at a second row and second column location during a second memory access cycle, said second memory access cycle immediately following the first memory access cycle, wherein performing comprises; determining if the second row is a same row as the first row; determining if the second column is a different column than the first column; and if both determinations are positive, then;
simultaneously within said second memory access cycle writing to the second cell and re-writing data from the first memory access cycle first write operation to the first cell. - View Dependent Claims (8, 9)
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10. A method, comprising:
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performing a write operation to a first cell of a memory array at a first row and first column location during a first memory access cycle; and performing a read operation from a second cell of the memory array at a second row and second column location during a second memory access cycle, said second memory access cycle immediately following the first memory access cycle, wherein performing comprises; determining if the second row is a same row as the first row; and if said determination is positive, then;
simultaneously within said second memory access cycle reading from the second cell and re-writing data from the first memory access cycle write operation to the first cell. - View Dependent Claims (11, 12, 13)
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14. A circuit, comprising:
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a memory array including a plurality of memory cells arranged in rows and columns; a control circuit configured to control read and write access to the memory array, said control circuit operable to; determine whether a write operation during a first memory access cycle to a first cell and a memory access operation during a second memory access cycle to a second cell share access to a same row and different column of the memory array, said second memory access cycle immediately following the first memory access cycle; and if there is a same row and the memory access operation is a read, or if there is a same row and different column and the memory access operation is a write, then;
simultaneously within said second memory access cycle access the second cell and re-write data from the first memory access cycle write operation to the first cell. - View Dependent Claims (15, 16, 17, 18, 19)
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20. A circuit, comprising:
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a memory array including a plurality of memory cells arranged in rows and columns; and a control circuit configured to control read and write access to the memory array, said control circuit operable to; determine whether a first write operation during a first memory access cycle to a first cell and a second write operation during a second memory access cycle to a second cell share access to a same row and different column of the memory array, said second memory access cycle immediately following the first memory access cycle; and if there is a same row and different column, then;
simultaneously within said second memory access cycle perform the write access operation on the second cell and perform a re-write of the data from the first memory access cycle write operation to the first cell. - View Dependent Claims (21)
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22. A circuit, comprising:
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a memory array including a plurality of memory cells arranged in rows and columns; and a control circuit configured to control read and write access to the memory array, said control circuit operable to; determine whether a write operation during a first memory access cycle to a first cell and a read access operation during a second memory access cycle to a second cell share access to a same row of the memory array, said second memory access cycle immediately following the first memory access cycle; and if there is a same row access operation is a read, then;
simultaneously within said second memory access cycle perform the read access operation on the second cell and perform a re-write of the data from the first memory access cycle write operation to the first cell. - View Dependent Claims (23, 24)
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Specification