Fuse element programming circuit and method

• US 9,324,448 B2
• Filed: 03/25/2014
• Issued: 04/26/2016
• Est. Priority Date: 03/25/2014
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Inventors: Hall, Jefferson W.
• Primary Examiner(s): Hur, J. H.
• Application Number:
  US14/225,272
• Publication Number:
  US 20150279478A1
• Time in Patent Office: 763 Days
• US Class Current: 1/1
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: G11C 17/18 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 5/147 Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops G11C5/141 takes precedence
• CPC Class Codes: H01L 23/5228 Resistive arrangements or effects of, or between, wiring layers other resistive arrangements H01L23/647
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 20/25 One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links
• CPC Class Codes: H10B 20/65 of memory structures of the ROM only type

Abstract

In one embodiment, a programming circuit is configured to form a programming current for a silicide fuse element by using a non-silicide programming element.

Claims

1. A circuit for programming a fuse element comprising:

a memory cell having the fuse element that includes a first semiconductor material body region and a silicide layer;

a programming circuit configured to form a programming current to program the fuse element; and

a programming element configured to control a value of the programming current, the programming element having a second semiconductor material body region but not a silicide layer;

the programming circuit configured to control the programming current to a first value responsively to a value of the fuse element and to subsequently control the programming current to a different value responsively to a value of the programming element.

2. The circuit of claim 1 wherein a resistivity of the programming element is substantially representative of a resistivity of the first semiconductor material body region of the fuse element.

3. The circuit of claim 1 wherein the programming element includes a doped polysilicon body region that is substantially devoid of a silicide material.

4. The circuit of claim 1 wherein the programming circuit includes a means for forming a value of the programming current to cause electro-migration of silicide material overlying a portion of the first semiconductor material body region of the fuse element and increasing a resistivity of the fuse element.

5. The circuit of claim 1 wherein the programming element includes a plurality of coupled sections wherein each section of the plurality of sections is substantially equal.

6. The circuit of claim 1 wherein the first and second semiconductor material body regions includes first and second polysilicon body regions.

7. The circuit of claim 1 wherein a resistivity of the programming element is substantially representative of a resistivity of the first semiconductor material body region of the fuse element prior to alloying the silicide layer with the first material semiconductor body region.

8. A method of forming a programming circuit for a fuse element comprising:

forming the fuse element having a first semiconductor layer and a silicide layer wherein the first semiconductor layer has a first resistivity and the silicide layer has a second resistivity; and

configuring the programming circuit to control a value of a programming current through the fuse element using a programming element having a third resistivity that is substantially the first resistivity;

configuring the programming circuit to form the programming current with a value to increase the first resistivity to a fourth resistivity and to decrease the programming current to a second value responsively to forming the fourth resistivity wherein the second value is greater than zero.

9. The method of claim 8 further including forming the programming element to include a second semiconductor layer wherein the programming element is substantially devoid of a silicide layer.

10. The method of claim 8 wherein configuring the programming circuit to control the value of the programming current includes configuring a control circuit to form the programming current to cause substantially a void in the silicide layer but not in the first semiconductor layer.

11. The method of claim 10 further including configuring the control circuit to form the programming current to increase the first resistivity to a fourth resistivity and substantially not form a void in the first semiconductor layer.