Nonvolatile memory

• US 9,324,457 B2
• Filed: 08/13/2014
• Issued: 04/26/2016
• Est. Priority Date: 03/12/2014
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Takizawa, Ryousuke
• Primary Examiner(s): LE, THONG QUOC
• Application Number:
  US14/458,872
• Publication Number:
  US 20150262701A1
• Time in Patent Office: 622 Days
• Field of Search: 365/148, 365/185.18, 365/154, 365/163, 365/185.02, 365/185.11, 365/185.21, 365/189.05, 365/200, 365/211
• US Class Current: 1/1
• CPC Class Codes: G11C 11/161 details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
• CPC Class Codes: G11C 11/1659 Cell access
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods
• CPC Class Codes: G11C 11/1675 Writing or programming circuits or methods
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: G11C 17/165 Memory cells which are electrically programmed to cause a change in resistance, e.g. to permit multiple resistance steps to be programmed rather than conduct to or from non-conduct change of fuses and antifuses digital stores using resistance random access memory elements G11C13/0002
• CPC Class Codes: G11C 2029/4402 Internal storage of test result, quality data, chip identification, repair information
• CPC Class Codes: G11C 29/70 Masking faults in memories by using spares or by reconfiguring

Abstract

According to one embodiment, a nonvolatile memory includes a memory area including a first magnetoresistive element, and a fuse circuit including a second magnetoresistive element serving as an anti-fuse element and configured to store correction information of the memory area when a defect exists in the memory area. The first magnetoresistive element includes a first storage layer, a first reference layer, and a first insulating film between the first storage layer and the first reference layer. The second magnetoresistive element includes a second storage layer, a second reference layer, and a second insulating film between the second storage layer and the second reference layer.

Claims

1. A nonvolatile memory comprising:

a memory area including a plurality of first magnetoresistive elements each serving as a memory element, each of the first magnetoresistive elements including a first storage layer, a first reference layer, and a first insulating film between the first storage layer and the first reference layer; and

a fuse circuit including a plurality of second magnetoresistive elements each serving as an anti-fuse element and configured to store correction information of the memory area when a defect exists in the memory area, each of the second magnetoresistive elements including a second storage layer, a second reference layer, and a second insulating film between the second storage layer and the second reference layer,

wherein;

a resistance value of each of the plurality of first magnetoresistive elements changes between a first resistance value and a second resistance value higher than the first resistance value,

each of the plurality of second magnetoresistive elements has one of the second resistance value and a third resistance value lower than the first resistance value, and

the second insulating film is broken in each second magnetoresistive element having the third resistance value among the plurality of second magnetoresistive elements.

2. The memory according to claim 1, further comprising:

a first read circuit configured to read data from at least a selected one among the plurality of first magnetoresistive elements using a first reference current as a determination criterion; and

a second read circuit configured to read data from at least a selected one among the plurality of second magnetoresistive elements using a second reference current different from the first reference current as a determination criterion.

3. The memory according to claim 2, wherein:

the first read circuit supplies a first read current to at least the selected one among the plurality of first magnetoresistive elements and supplies the first reference current to a first reference cell,

the second read circuit supplies a second read current to at least the selected one among the plurality of second magnetoresistive elements and supplies the second reference current to a second reference cell,

a magnitude of the first read current is controlled by a first clamp voltage,

a magnitude of the first reference current is controlled by a second clamp voltage different from the first clamp voltage,

a magnitude of the second read current and a magnitude of the second reference current are controlled by a third clamp voltage,

the first reference current is set based on an average value of the first resistance value and the second resistance value, and has a current value smaller than a current value that changes a resistance value of the selected one among the plurality of first magnetoresistive elements to the first resistance value, and

the second reference current has a current value set based on the first resistance value.

4. The memory according to claim 1, further comprising:

a first write circuit configured to bidirectionally supply a first write current to at least a selected one among the plurality of first magnetoresistive elements, and including a first source circuit configured to change a resistance value of at least the selected one among the plurality of first magnetoresistive elements to the first resistance value, and a second source circuit configured to change a resistance value of at least the selected one among the plurality of first magnetoresistive elements to the second resistance value; and

a second write circuit configured to unidirectionally supply a second write current to at least one among the plurality of second magnetoresistive elements, and including a third source circuit configured to set a resistance value of at least a selected one among the plurality of second magnetoresistive elements to the second resistance value, and a fourth source circuit configured to set a resistance value of at least the selected one among the plurality of second magnetoresistive elements to the third resistance value,

wherein an output of the third source circuit has a same magnitude as an output of the second source circuit, and an output of the fourth source circuit is larger than the output of the second source circuit.

5. The memory according to claim 4, wherein the fourth source circuit is connected to an external power supply terminal.

6. The memory according to claim 1, further comprising a third read circuit shared by data read for the plurality of first magnetoresistive elements and data read for the plurality of second magnetoresistive elements,

wherein:

the memory area is provided in a cell array, and

the plurality of second magnetoresistive elements are provided in the cell array so as to be adjacent to the memory area.

7. The memory according to claim 1, wherein a size of each of the plurality of second magnetoresistive elements is larger than a size of each of the plurality of first magnetoresistive elements.

8. The memory according to claim 1, wherein:

each of the plurality of first magnetoresistive elements further includes a first magmatic layer including a magnetization facing opposite to a magnetization direction of the first reference layer,

each of the plurality of second magnetoresistive elements further includes a second magmatic layer including a magnetization facing opposite to the magnetization direction of the second reference layer, and

a size of the second magmatic layer in a direction parallel to a film surface of the second magmatic layer is larger than a size of the first magmatic layer in a direction parallel to a film surface of the first magmatic layer.

9. The memory according to claim 1, further comprising a redundancy area including a plurality of third magnetoresistive elements each serving as a redundancy element, each of the third magnetoresistive elements including a third storage layer, a third reference layer, and a third insulating film between the third storage layer and the third reference layer,

wherein when an external address signal matches the correction information, one third magnetoresistive element among the plurality of third magnetoresistive elements is selected.

10. A nonvolatile memory comprising:

a first memory area including a plurality of first magnetoresistive elements, each of the first magnetoresistive elements including a first storage layer, a first reference layer, and a first insulating film between the first storage layer and the first reference layer; and

a second memory area including a plurality of second magnetoresistive elements, each of the second magnetoresistive elements including a second storage layer, a second reference layer, and a second insulating film between the second storage layer and the second reference layer,

wherein;

when a defect exists in the first memory area, the second memory area stores correction information of the first memory area,

a resistance value of each of the plurality of first magnetoresistive elements changes between a first resistance value and a second resistance value higher than the first resistance value,

each of the plurality of second magnetoresistive elements has one of the second resistance value and a third resistance value lower than the first resistance value, and

the second insulating film is broken in each second magnetoresistive element having the third resistance value among the plurality of second magnetoresistive elements.

11. A nonvolatile memory comprising:

a memory area including a plurality of first magnetoresistive elements each serving as a memory element, each of the first magnetoresistive elements including a first storage layer, a first reference layer, and a first insulating film between the first storage layer and the first reference layer; and

a fuse circuit including a plurality of second magnetoresistive elements each serving as an anti-fuse element and configured to store correction information of the memory area when a defect exists in the memory area, each of the second magnetoresistive elements including a second storage layer, a second reference layer, and a second insulating film between the second storage layer and the second reference layer,

wherein the fuse circuit includes a plurality of fuse elements each configured to store at least part of the correction information.

12. The memory according to claim 11, further comprising a plurality of registers a number of which is as large as at least one of a number of the plurality of fuse elements and a number of the plurality of second magnetoresistive elements, wherein the plurality of registers are configured to store data of the plurality of the fuse elements and the plurality of second magnetoresistive elements.

13. The memory according to claim 12, wherein the number of the plurality of fuse elements equals the number of registers.

14. The memory according to claim 11, wherein the fuse circuit writes data stored in the plurality of fuse elements to the plurality of second magnetoresistive elements.

15. The memory according to claim 11, wherein:

the fuse circuit has error correcting capability and includes an encoding circuit configured to encode data stored in the plurality of fuse elements, and a decoding circuit configured to decode data read from the plurality of second magnetoresistive elements, and

the encoded data of the plurality of fuse elements are stored in the second magnetoresistive elements.

16. The memory according to claim 11, wherein the fuse circuit includes a comparator configured to compare data stored in the plurality of fuse elements and data stored in the plurality of second magnetoresistive elements.

17. The memory according to claim 16, wherein after the correction information is written in the fuse circuit, a write operation for setting a resistance value of each of the plurality of second magnetoresistive elements to the second resistance value is executed.

18. The memory according to claim 11, further comprising a third read circuit shared by data read for the plurality of first magnetoresistive elements and data read for the plurality of second magnetoresistive elements,

wherein:

the memory area is provided in a cell array, and

the plurality of second magnetoresistive elements are provided in the cell array so as to be adjacent to the memory area.

19. The memory according to claim 11, wherein a size of each of the plurality of second magnetoresistive elements is larger than a size of each of the plurality of first magnetoresistive elements.

20. The memory according to claim 11, wherein:

each of the plurality of first magnetoresistive elements further includes a first magmatic layer including a magnetization facing opposite to a magnetization direction of the first reference layer,

each of the plurality of second magnetoresistive elements further includes a second magmatic layer including a magnetization facing opposite to the magnetization direction of the second reference layer, and

a size of the second magmatic layer in a direction parallel to a film surface of the second magmatic layer is larger than a size of the first magmatic layer in a direction parallel to a film surface of the first magmatic layer.