Method of fabricating a vertically oriented inductor within interconnect structures and capacitor structure thereof

• US 9,324,605 B2
• Filed: 09/15/2014
• Issued: 04/26/2016
• Est. Priority Date: 08/18/2011
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Cho, Hsiu-Ying
• Primary Examiner(s): Tran, Minh-Loan
• Assistant Examiner(s): KHAN, FARID H
• Application Number:
  US14/486,675
• Publication Number:
  US 20150004770A1
• Time in Patent Office: 589 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/768 Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 23/5225 Shielding layers formed together with wiring layers
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 25/16 the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

The present disclosure involves a method of fabricating a semiconductor device. The method includes providing a substrate having a horizontal surface. The method includes forming an interconnect structure over the horizontal surface of the substrate. The forming the interconnect structure includes forming an inductor coil that is wound substantially in a vertical plane that is orthogonal to the horizontal surface of the substrate. The forming the interconnect structure includes forming a capacitor disposed proximate to the inductor coil. The capacitor has an anode component and a cathode component. The inductor coil and the capacitor each include a plurality of horizontally extending elongate members.

Claims

1. A method of fabricating a semiconductor device, comprising:

providing a substrate having a surface that spans in an X direction and a Y direction that is perpendicular to the X direction; and

forming an interconnect structure over the surface of the substrate, the interconnect structure having a plurality of conductive lines interconnected by a plurality of vias, wherein the forming the interconnect structure includes forming an inductor capacitor (LC) tank using a subset of the conductive lines and a subset of the vias;

wherein;

the LC tank includes an inductor that is formed to have a coil winding orientation that at least in part spans a Z direction that is perpendicular to the X and Y directions;

the LC tank includes a capacitor that is formed to have an anode component and a cathode component that is interdigitated with the anode component; and

the inductor and the capacitor are interdigitated.

2. The method of claim 1, wherein the forming the LC tank is carried out in a manner such that the conductive lines of the inductor and capacitor each extend in a direction parallel to the surface of the substrate.

3. The method of claim 1, wherein the forming the LC tank is carried out in a manner such that the conductive lines of the inductor are perpendicular to the conductive lines of the capacitor.

4. The method of claim 1, wherein the forming the LC tank is carried out in a manner such that the capacitor is partially surrounded by the inductor.

5. The method of claim 1, further including forming a shielding structure that surrounds the LC tank, wherein the shielding structure includes a plurality of elongate lines.

6. A method of fabricating a semiconductor device, comprising:

providing a substrate having a horizontal surface; and

forming an interconnect structure over the horizontal surface of the substrate, the forming the interconnect structure including;

forming an inductor coil that is wound substantially in a vertical plane that is orthogonal to the horizontal surface of the substrate; and

forming a capacitor disposed proximate to the inductor coil, the capacitor having an anode component and a cathode component;

wherein the inductor coil and the capacitor each include a plurality of horizontally extending elongate members; and

wherein;

the inductor coil and the capacitor are interdigitated.

7. The method of claim 6, wherein the forming the interconnect structure further includes:

forming a plurality of metal lines disposed in a plurality of interconnect layers;

wherein the elongate members of the inductor coil and the elongate members of the capacitor each include a respective subset of the metal lines.

8. The method of claim 7, wherein the forming the interconnect structure further includes:

forming a plurality of via stacks;

wherein the inductor coil includes a subset of the via stacks that interconnect the elongate members of the inductor coil together.

9. The method of claim 6, wherein at least some of the elongate members of the capacitor are surrounded by the inductor coil.

10. The method of claim 6, wherein the elongate members of the inductor coil are perpendicular to the elongate members of the capacitor.

11. The method of claim 6, wherein the elongate members of the anode component are interdigitated with the elongate members of the cathode component.

12. A method of fabricating a semiconductor device, comprising:

providing a substrate having a surface that is defined by a first axis and a second axis that is perpendicular to the first axis;

forming an inductor over the surface of the substrate, the inductor having a coil that is wound at least in part vertically about a third axis that is perpendicular to the first axis and the second axis; and

forming a capacitor over the substrate and adjacent to the inductor; and

wherein;

the inductor and the capacitor are interdigitated.

13. The method of claim 12, further comprising forming an interconnect structure over the surface of the substrate, wherein the inductor and capacitor are disposed within the interconnect structure.

14. The method of claim 13, wherein the forming the interconnect structure further includes forming a plurality of conductive lines and a plurality of conductive vias, wherein the inductor and the capacitor are each implemented using a respective subset of the conductive lines and conductive vias.

15. The method of claim 14, wherein the conductive lines of the inductor are perpendicular to the conductive lines of the capacitor.

16. The method of claim 12, wherein the inductor has an associated magnetic field that is substantially parallel to the surface of the substrate.

17. The method of claim 12, wherein the surface of the substrate is a horizontal surface, and the winding orientation of the inductor is a vertical winding orientation.

18. The method of claim 12, further comprising forming a dielectric material that separates the inductor and the capacitor.

19. The method of claim 12, further comprising forming a shielding structure that includes a plurality of strip lines, wherein the inductor and the capacitor are shielded by the shielding structure.