Compact wirebonded power quad flat no-lead (PQFN) package

• US 9,324,638 B2
• Filed: 10/26/2012
• Issued: 04/26/2016
• Est. Priority Date: 12/13/2010
• Status: Active Grant

• Current Assignee: Infineon Technologies Americas Corp. (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Americas Corp. (Infineon Technologies AG)
• Inventors: Fernando, Dean, Barbosa, Roel
• Primary Examiner(s): Gumedzoe, Peniel M
• Application Number:
  US13/662,244
• Publication Number:
  US 20130105958A1
• Time in Patent Office: 1,278 Days
• Field of Search: 257/578, 257/677, 257/690, 257/723, 257/E23.031, 257/E23.042, 257/E23.052, 257/E23.061
• US Class Current: 1/1
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/45147 Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/4903 Connectors having different sizes, e.g. different diameters
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 23/3107 the device being completely enclosed
• CPC Class Codes: H01L 23/49513 having bonding material between chip and die pad
• CPC Class Codes: H01L 23/4952 the additional leads being a bump or a wire
• CPC Class Codes: H01L 23/49541 Geometry of the lead-frame
• CPC Class Codes: H01L 23/49548 Cross section geometry H01L23/49562 takes precedence
• CPC Class Codes: H01L 23/49562 for devices being provided for in H01L29/00
• CPC Class Codes: H01L 23/49575 Assemblies of semiconductor devices on lead frames
• CPC Class Codes: H01L 24/32 of an individual layer connector
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13055 : Insulated gate bipolar transistor [IGBT]
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/18301 : being an anchoring portion, i.e. mechanical interlocking between the encapsulation resin and another package part
• CPC Class Codes: H01L 2924/20753 : larger or equal to 30 microns less than 40 microns
• CPC Class Codes: H01L 2924/20755 : larger or equal to 50 microns less than 60 microns
• CPC Class Codes: H01L 2924/3512 : Cracking

Abstract

Some exemplary embodiments of a multi-chip module (MCM) power quad flat no-lead (PQFN) semiconductor package utilizing a leadframe for electrical interconnections have been disclosed. One exemplary embodiment comprises a PQFN semiconductor package comprising a leadframe, a driver integrated circuit (IC) coupled to the leadframe, a plurality of vertical conduction power devices coupled to the leadframe, and a plurality of wirebonds providing electrical interconnects, including at least one wirebond from a top surface electrode of one of the plurality of vertical conduction power devices to a portion of the leadframe, wherein the portion of the leadframe is electrically connected to a bottom surface electrode of another of the plurality of vertical conduction power devices. In this manner, efficient multi-chip circuit interconnections can be provided in a PQFN package using low cost leadframes.

Claims

1. A power quad flat no-lead (PQFN) package comprising:

a first wirebond connecting a source electrode of a first vertical conduction power device to a plating on a leadframe, said plating connecting to a drain electrode of a second vertical conduction power device through said leadframe;

a second wirebond connecting a source electrode of a third vertical conduction power device to a drain electrode of a fourth vertical conduction power device through said leadframe;

a third wirebond directly connected between a source electrode of a fifth vertical conduction power device and a projection of a die pad of said leadframe, said projection of said die pad terminating within said PQFN package, a sixth vertical conduction power device having a drain electrode situated on said die pad;

wherein a routing path between said first vertical conduction power device and said second vertical conduction power device is longer than a routing path between said fifth vertical conduction power device and said sixth vertical conduction power device;

a driver integrated circuit (IC) situated within said PQFN package.

2. The PQFN package of claim 1, wherein the first, third, and fifth vertical conduction power devices comprise high side field-effect transistors (FETs) of a full bridge power device.

3. The PQFN package of claim 1, wherein the first, third, and fifth vertical conduction power devices comprise high side field-effect transistors (FETs) of a full bridge power device.

4. The PQFN package of claim 1, wherein said driver IC is coupled to said leadframe, said driver IC connected to drive said first, second, third, fourth, fifth, and sixth vertical conduction power devices.

5. The PQFN package of claim 1, wherein said first wirebond is connected between said source electrode of said first vertical conduction power device and a first leadframe portion of said leadframe.

6. The PQFN package of claim 1, wherein said second wirebond is connected between said source electrode of said third vertical conduction power device and a second leadframe portion of said leadframe.

7. The PQFN package of claim 1, wherein drain electrodes of said first, third, and fifth vertical conduction power devices are coupled to a same die pad of said leadframe.

8. The PQFN package of claim 1, wherein drain electrodes of said second, fourth, and sixth vertical conduction power devices are individually coupled to corresponding die pads of said leadframe.

9. The PQFN package of claim 1, wherein said first, third, and fifth vertical conduction power devices are positioned along a first edge of said PQFN package.

10. The PQFN package of claim 1, wherein said second, fourth, and sixth vertical conduction power devices are positioned along a second edge of said PQFN package.

11. A power quad flat no-lead (PQFN) package comprising:

a source electrode of a first vertical conduction power device connected to a plating on a leadframe, said plating connecting to a drain electrode of a second vertical conduction power device through a first leadframe portion;

a source electrode of a third vertical conduction power device connected to a drain electrode of a fourth vertical conduction power device through a second leadframe portion;

a source electrode of a fifth vertical conduction power device directly wirebonded to a projection of a die pad, said projection of said die pad terminating within said PQFN package, a sixth vertical conduction power device having a drain electrode situated on said die pad;

wherein a routing path between said first vertical conduction power device and said second vertical conduction power device is longer than a routing path between said fifth vertical conduction power device and said sixth vertical conduction power device;

a driver integrated circuit (IC) situated within said PQFN package.

12. The PQFN package of claim 11, wherein the first, third, and fifth vertical conduction power devices comprise high side field-effect transistors (FETs) of a full bridge power device.

13. The PQFN package of claim 11, wherein the first, third, and fifth vertical conduction power devices comprise high side field-effect transistors (FETs) of a full bridge power device.

14. The PQFN package of claim 11, wherein said driver IC is wirebonded to respective gate electrodes of said first, second, third, fourth, fifth, and sixth vertical conduction power devices.

15. The PQFN package of claim 11, comprising a first wirebond connected between said source electrode of said first vertical conduction power device and said first leadframe portion.

16. The PQFN package of claim 11, comprising a second wirebond connected between said source electrode of said third vertical conduction power device and said second leadframe portion.

17. The PQFN package of claim 11, wherein drain electrodes of said first, third, and fifth vertical conduction power devices are coupled to a first die pad.

18. The PQFN package of claim 11, wherein drain electrodes of said second, fourth, and sixth vertical conduction power devices are individually coupled to corresponding die pads.

19. The PQFN package of claim 11, wherein said first, third, and fifth vertical conduction power devices are positioned along a first edge of said PQFN package.

20. The PQFN package of claim 11, wherein said second, fourth, and sixth vertical conduction power devices are positioned along a second edge of said PQFN package.