Pin attachment

• US 9,324,681 B2
• Filed: 09/26/2014
• Issued: 04/26/2016
• Est. Priority Date: 12/13/2010
• Status: Active Grant

• Current Assignee: Tessera, Inc. (Adeia Inc.)
• Original Assignee: Tessera, Inc. (Adeia Inc.)
• Inventors: Haba, Belgacem, Mohammed, Ilyas
• Primary Examiner(s): Crawford, Latanya N
• Application Number:
  US14/497,572
• Publication Number:
  US 20150011052A1
• Time in Patent Office: 578 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/4853 Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 2224/11003 for holding or transferring the bump preform
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/811 the bump connector being supplied to the parts to be connected in the bonding apparatus
• CPC Class Codes: H01L 2224/81801 Soldering or alloying
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/1023 the support being an insulating substrate
• CPC Class Codes: H01L 2225/1058 Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 2225/1088 Arrangements to limit the height of the assembly
• CPC Class Codes: H01L 23/3121 a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/49811 Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15331 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/207 : Diameter ranges

Abstract

A method for making a microelectronic package includes the steps of providing a microelectronic assembly that further includes a substrate with a plurality of conductive elements thereon, a carrier, and a plurality of substantially rigid metal elements extending from the carrier and joined to the conductive elements; and removing the carrier from the microelectronic assembly to expose contact surfaces of the respective ones of the plurality of metal elements remote from the first conductive pads.

Claims

1. A method for making a microelectronic package, comprising:

providing a microelectronic assembly including a first substrate having a first surface with a plurality of electrically conductive elements exposed thereon, a carrier having a second surface spaced apart from the first surface of the substrate, and a plurality of substantially rigid metal elements extending from the carrier and joined to the electrically conductive elements, the first surface of the first substrate including first and second regions, the electrically conductive elements being exposed at the first surface within the first region;

injecting a dielectric material between the first and second surfaces and around the plurality of substantially rigid metal elements to form a molded dielectric layer;

removing the carrier from the microelectronic assembly, thereby exposing contact surfaces of respective ones of the plurality of substantially rigid metal elements remote from the plurality of electrically conductive elements; and

affixing a microelectronic element to the first substrate and electronically connecting the microelectronic element to at least some of the electrically conductive elements after the step of removing the carrier,

wherein the microelectronic element is attached on the first surface within the second region, and wherein the molded dielectric layer is formed in a first dielectric layer portion and a second dielectric layer portion by the steps of;

forming the first dielectric layer portion over the first region of the first surface prior to the step of attaching the microelectronic element; and

forming the second dielectric layer portion over the second region of the first surface after the step of attaching the microelectronic element.

2. The method of claim 1, wherein the step of injecting is prior to the step of removing the carrier.

3. The method of claim 1, wherein each of the plurality of substantially rigid metal elements are joined to respective ones of the conductive elements through a bond metal.

4. The method of claim 1, wherein the step of removing the carrier includes at least one of etching, lapping or peeling the carrier.

5. The method of claim 1, further including forming the microelectronic assembly from a first subassembly including the first substrate and the conductive elements and a second subassembly including the carrier and the plurality of substantially rigid metal elements, wherein the plurality of substantially rigid metal elements are exposed at first surfaces remote from the second surface, and wherein the microelectronic assembly is formed by attaching the first surfaces of the plurality of substantially rigid metal elements to the conductive elements of the second subassembly.

6. The method of claim 5, wherein the step of forming the first microelectronic assembly includes attaching at least the first surfaces of the plurality of substantially rigid metal elements to the plurality of conductive elements of the second assembly by forming a plurality of masses of a bonding metal that are affixed to the first surfaces of the conductive projections and to respective ones of the conductive elements such that at least a portion of the bonding metal is disposed between the first surfaces and the conductive elements.

7. The method of claim 6, wherein the bonding metal masses are formed by depositing solder on one of the group consisting of the conductive projections and the conductive elements.

8. The method of claim 1, wherein the microelectronic assembly further includes a microelectronic element affixed on the substrate and electronically connected to at least some of the conductive elements.

9. The method of claim 8, wherein the microelectronic element is included in the microelectronic assembly by a step of affixing the microelectronic element on the first substrate carried out prior to the step of removing the carrier.

10. The method of claim 8, wherein the first surface of the first substrate includes first and second regions, the conductive elements being exposed at the first surface within the first region and the microelectronic element being attached on the first surface within the second region, the method further including molding a dielectric layer over the first and second regions of the first surface and at least a portion of said microelectronic element, wherein the molded dielectric layer includes an outer surface, and wherein the contact surfaces of the plurality of substantially rigid metal elements are exposed at the outer surface of the molded dielectric layer.

11. The method of claim 5, wherein the second subassembly is formed by a method including the step of forming the plurality of substantially rigid metal elements on the second surface of the carrier.

12. The method of claim 11, wherein the step of forming the plurality of substantially rigid metal elements includes selectively etching a metal layer on a carrier such that selected portions of the metal layer form the plurality of substantially rigid metal elements.

13. The method of claim 1, wherein the microelectronic assembly is formed by the steps of:

depositing a plurality of masses of a bonding metal on the conductive elements; and

affixing a structure to the plurality of masses, the structure including the carrier and a rigid metal layer, such that the plurality of masses are exposed at selected areas of the rigid metal layer that form the plurality of substantially rigid metal elements.

14. A method for making a microelectronic package, comprising:

providing a microelectronic assembly including a first substrate having a first surface with a plurality of electrically conductive elements exposed thereon, a carrier having a second surface spaced apart from the first surface of the first substrate, and a plurality of substantially rigid metal elements extending from the carrier and joined to the conductive elements;

forming the microelectronic assembly from a first subassembly including the first substrate and the conductive elements and a second subassembly including the carrier and a plurality of substantially rigidmetal elements formed on the second surface of the carrier, the second subassembly being formed by affixing a rigid metal layer to the second surface of the carrier and depositing a mask layer having a plurality of openings therethrough over the rigid metal layer, the plurality of openings exposing the selected portions of the rigid metal layer, depositing masses of a bonding metal within the plurality of openings and along selected portions of the rigid metal layer such that outer surfaces are defined on the masses of the bonding metal, and removing areas of the rigid metal layer outside of the selected portions thereof; and

removing the carrier from the microelectronic assembly, thereby exposing contact surfaces of respective ones of the plurality of rigid metal elements remote from the plurality of electrically conductive elements,

wherein the plurality of substantially rigid metal elements are exposed at the outer surfaces remote from the second surface of the carrier, and wherein the microelectronic assembly is formed by attaching the outer surfaces of the plurality of substantially rigid metal elements to the conductive elements of first subassembly.

15. The method of claim 14, further including the step of removing the mask layer.

16. The method of claim 14, wherein the mask layer acts as at least a portion of an encapsulant layer after the step of transferring the plurality of substantially rigid metal elements.