Method and system for height registration during chip bonding

• US 9,324,682 B2
• Filed: 04/25/2014
• Issued: 04/26/2016
• Est. Priority Date: 04/25/2013
• Status: Active Grant

• Current Assignee: Skorpios Technologies Inc.
• Original Assignee: Skorpios Technologies Inc.
• Inventors: Marchena, Elton, Spann, John Y., Creazzo, Timothy, Krasulick, Stephen B., Mizrahi, Amit
• Primary Examiner(s): Lee, Hsien Ming
• Application Number:
  US14/262,529
• Publication Number:
  US 20140319656A1
• Time in Patent Office: 732 Days
• Field of Search: 438/26, 438/27, 438/29, 438/69, 438/106, 385/14, 385/129, 385/130
• US Class Current: 1/1
• CPC Class Codes: G02B 6/423 using guiding surfaces for the alignment
• CPC Class Codes: G02B 6/4238 Soldering
• CPC Class Codes: H01L 2224/29036 covering only the central area of the surface to be connected
• CPC Class Codes: H01L 2224/29109 Indium [In] as principal constituent
• CPC Class Codes: H01L 2224/8114 Guiding structures outside the body
• CPC Class Codes: H01L 2224/8314 Guiding structures outside the body
• CPC Class Codes: H01L 2224/83193 wherein the layer connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/83345 Shape, e.g. interlocking features
• CPC Class Codes: H01L 23/13 characterised by the shape
• CPC Class Codes: H01L 24/29 of an individual layer connector
• CPC Class Codes: H01L 24/32 of an individual layer connector
• CPC Class Codes: H01L 24/83 using a layer connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01046 Palladium [Pd]
• CPC Class Codes: H01L 2924/12042 LASER
• CPC Class Codes: H01S 5/021 Silicon based substrates
• CPC Class Codes: H01S 5/02326 Arrangements for relative positioning of laser diodes and optical components, e.g. grooves in the mount to fix optical fibres or lenses
• CPC Class Codes: H01S 5/0237 by soldering

Abstract

A method of fabricating a composite semiconductor structure is provided. Pedestals are formed in a recess of a first substrate. A second substrate is then placed within the recess in contact with the pedestals. The pedestals have a predetermined height so that a device layer within the second substrate aligns with a waveguide of the first substrate, where the waveguide extends from an inner wall of the recess.

Claims

1. A method of fabricating a composite semiconductor device, the method comprising:

providing a first semiconductor structure comprising a first material, wherein the first material is silicon, and having;

a first surface in a first recess;

a first waveguide extending to a wall of the first recess, the first waveguide at a first predetermined height above the first surface;

a third surface in a second recess; and

a second waveguide extending to a wall of the second recess, the second waveguide at the first predetermined height above the third surface;

forming a base portion of a pedestal in the first recess extending to a second predetermined height in a direction normal to the first surface;

forming a base portion of a pedestal in the second recess extending to the second predetermined height in a direction normal to the third surface;

providing a second semiconductor structure comprising a second material, wherein the second material is a III-V compound, and having;

a second surface; and

a device layer above the second surface;

providing a third semiconductor structure comprising a fourth material, wherein the fourth material is a III-V compound, and having;

a fourth surface; and

a device layer above the fourth surface;

placing a first thickness of a third material on the base portion of the pedestal in the first recess;

placing a second thickness of the third material on the base portion of the pedestal in the second recess;

placing the second semiconductor structure in the first recess of the first semiconductor structure;

bonding the second surface of the second semiconductor structure to the first surface of the first semiconductor structure, wherein the second surface of the second semiconductor structure contacts a top surface of the pedestal in the first recess such that the device layer of the second semiconductor structure is aligned with the first waveguide of the first semiconductor structure;

placing the third semiconductor structure in the second recess of the first semiconductor structure; and

bonding the fourth surface of the third semiconductor structure to the third surface of the first semiconductor structure, wherein the fourth surface of the third semiconductor structure contacts a top surface of the pedestal in the second recess such that the device layer of the third semiconductor structure is aligned with the second waveguide of the first semiconductor structure.

2. The method of claim 1, wherein:

the pedestal in the first recess has a height h above the first surface;

the first waveguide has a height x above the first surface; and

the device layer of the second semiconductor device has a height x−

h above the second surface.

3. The method of claim 1, further comprising:

depositing a bonding material on the first surface around the pedestal in the first recess before joining the first semiconductor structure and the second semiconductor structure.

4. The method of claim 1, further comprising depositing a bonding material on the second surface before joining the first semiconductor structure and the second semiconductor structure.

5. The method of claim 1, wherein the base portion of the pedestal in the first recess is formed from the first material.

6. The method of claim 1, wherein bonding the second surface of the second semiconductor structure to the first surface of the first semiconductor structure uses a bonding material comprising a metal.

7. The method of claim 1, wherein the base portion of the pedestal in the first recess is formed by etching the first semiconductor structure.

8. The method of claim 7, wherein a top of the base portion of the pedestal in the first recess is defined by etching to a location of an interface between the first material and another material.

9. A composite semiconductor device, the device comprising:

a first semiconductor structure comprising a first material, wherein the first material is silicon, and having;

a first surface in a first recess;

a first waveguide extending to a wall of the first recess, wherein the first waveguide is at a first predetermined height above the first surface;

a base portion of a pedestal in the first recess extending to a second predetermined height in a direction normal to the first surface; and

a first thickness of a third material on the base portion of the pedestal in the first recess;

a second semiconductor structure comprising a second material, wherein the second material is a III-V compound, and having;

a device layer; and

a second surface below the device layer, wherein;

the second surface of the second semiconductor structure is bonded to the first surface of the first semiconductor structure such that the second semiconductor structure is secured in the first recess of the first semiconductor structure; and

the second surface of the second semiconductor structure contacts a top surface of the pedestal in the first recess such that the device layer of the second semiconductor device is aligned with the first waveguide of the first semiconductor structure;

a third semiconductor structure comprising the first material and having;

a third surface in a second recess;

a second waveguide extending to a wall of the second recess, the second waveguide at the first predetermined height above the third surface;

a base portion of the pedestal in the second recess extending to the second predetermined height in a direction normal to the third surface; and

a second thickness of the third material on the base portion of the pedestal in the second recess; and

a fourth semiconductor structure comprising the second material and having;

a device layer; and

a fourth surface below the device layer, wherein;

the fourth surface of the fourth semiconductor structure is bonded to the third surface of the third semiconductor structure such that the fourth semiconductor structure is secured in the second recess of the third semiconductor structure; and

the fourth surface of the fourth semiconductor structure contacts a top surface of the pedestal in the second recess such that the device layer of the fourth semiconductor device is aligned with the second waveguide of the third semiconductor structure.

10. The composite semiconductor device of claim 9, wherein the first recess with the first surface was formed by etching the first semiconductor structure.

11. The composite semiconductor device of claim 9, wherein:

the pedestal of the first recess has a height h above the first surface;

the first waveguide has a height x above the first surface; and

the device layer of the second semiconductor device has a height x−

h above the second surface.

12. The composite semiconductor device of claim 9, wherein there are at least five pedestals in the first recess.

13. A method of fabricating pedestals for a composite semiconductor structure, the method comprising:

providing a first semiconductor structure comprising a first material and having;

a first recess with a first bottom surface;

a first waveguide extending to a wall of the first recess, the first waveguide at a first predetermined height above the first bottom surface; and

a base portion of a first pedestal having a second predetermined height;

placing a first thickness of a third material on the base portion of the first pedestal of the first semiconductor structure to form the first pedestal, wherein;

the first pedestal aligns a first chip with the first waveguide; and

the first chip comprises a second material;

providing a second semiconductor structure comprising the first material and having;

a second recess with a second bottom surface;

a second waveguide extending to a wall of the second recess, the second waveguide at the first predetermined height above the second bottom surface; and

a base portion of a second pedestal having the second predetermined height; and

placing a second thickness of the third material on the base portion of the second pedestal forming the second pedestal, wherein;

the second pedestal of the second semiconductor structure aligns a second chip with the second waveguide; and

the second chip comprises a fourth material.

14. The method of claim 13, wherein the fourth material is the same as the second material.

15. The method of claim 13, wherein the first material is silicon and the second material is a III-V compound.

16. The method of claim 13, further comprising depositing a bonding material on the first bottom surface around the first pedestal of the first semiconductor structure before joining the first semiconductor structure and the first chip.