Wafer-level passive device integration

• US 9,324,687 B1
• Filed: 06/28/2013
• Issued: 04/26/2016
• Est. Priority Date: 03/14/2013
• Status: Active Grant

• Current Assignee: Maxim Integrated Products, Inc. (Analog Devices, Inc.)
• Original Assignee: Maxim Integrated Products, Inc. (Analog Devices, Inc.)
• Inventors: Kelkar, Amit S., Thambidurai, Karthik, Harper, Peter R., Khandekar, Viren
• Primary Examiner(s): McCall Shepard, Sonya D
• Application Number:
  US13/930,601
• Time in Patent Office: 1,033 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/2919 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32265 the item being a discrete passive component
• CPC Class Codes: H01L 2224/48145 the bodies being stacked
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73209 Bump and HDI connectors
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/83 using a layer connector
• CPC Class Codes: H01L 2224/92124 the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 2224/92125 the second connecting process involving a layer connector
• CPC Class Codes: H01L 2224/92225 the second connecting process involving a layer connector
• CPC Class Codes: H01L 2224/94 at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 23/3114 : the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 : Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 24/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/16 : the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/19104 : on the semiconductor or solid-state device, i.e. passive-on-chip
• CPC Class Codes: H01L 2924/19105 : in a side-by-side arrangement on a common die mounting substrate

Abstract

A device and fabrication techniques are described that employ wafer-level packaging techniques to fabricate semiconductor devices that include an embedded integrated circuit chip device and an embedded passive device on a semiconductor wafer device. In implementations, the wafer-level package device includes a semiconductor wafer device, an embedded integrated circuit chip, an embedded passive device, an encapsulation structure covering at least a portion of the semiconductor wafer device, the embedded integrated circuit chip, and the embedded passive device, at least one redistribution layer structure, and at least one solder bump for providing electrical interconnectivity to the devices. Once the wafer is singulated into semiconductor devices, the semiconductor devices may be mounted to a printed circuit board, and the solder bumps may provide electrical interconnectivity through the backside of the device that interface with pads of the printed circuit board.

Claims

1. A wafer-level package device comprising:

a segmented semiconductor wafer section configured to function as a base layer;

an integrated circuit chip device coupled to the segmented semiconductor wafer section;

a passive device disposed proximate to the integrated circuit chip device and coupled to the segmented semiconductor wafer section;

at least one pillar electrically coupled to the integrated circuit chip device and at least one pillar electrically coupled to the passive device;

an encapsulation layer covering at least a portion of the segmented semiconductor wafer section, the integrated circuit chip device, and the passive device;

a redistribution layer structure coupled to the at least one pillar; and

at least one solder bump coupled to the redistribution layer structure and disposed on a surface of the encapsulation layer distal from the segmented semiconductor wafer section.

2. The wafer-level package device as recited in claim 1, wherein the segmented semiconductor wafer section includes a silicon wafer.

3. The wafer-level package device as recited in claim 1, wherein the encapsulation layer includes an epoxy overmold.

4. The wafer-level package device as recited in claim 1, wherein the at least one pillar includes at least one copper pillar.

5. The wafer-level package device as recited in claim 1, wherein the passive device includes a passive device with at least one copper pillar configured to provide an electrical interconnection.

6. The wafer-level package device as recited in claim 1, wherein the passive device includes a passive device that is electrically connected with the integrated circuit chip device.

7. The wafer-level package device as recited in claim 1, wherein the passive device includes a resistor.

8. The wafer-level package device as recited in claim 1, wherein the passive device includes a capacitor.

9. An electronic device comprising:

a printed circuit board; and

a wafer level-package device coupled to the printed circuit board, the wafer-level package device including

a segmented semiconductor wafer section configured to function as a base layer;

an integrated circuit chip device coupled to the segmented semiconductor wafer section;

a passive device coupled to the segmented semiconductor wafer section and disposed proximate to the integrated circuit chip device;

at least one pillar coupled to the integrated circuit chip device and configured to provide an electrical interconnection to the integrated circuit chip device;

an encapsulation layer covering at least a portion of the segmented semiconductor wafer section, the integrated circuit chip device, and the passive device;

a redistribution layer structure coupled to at least the integrated circuit chip device; and

at least one solder bump coupled to the redistribution layer structure and disposed on a surface of the encapsulation layer distal from the segmented semiconductor wafer section.

10. The electronic device as recited in claim 9, wherein the segmented semiconductor wafer section includes a silicon carrier.

11. The electronic device as recited in claim 9, wherein the at least one pillar includes at least one copper pillar.

12. The electronic device as recited in claim 9, wherein the encapsulation layer includes an epoxy overmold.

13. The electronic device as recited in claim 9, wherein the passive device includes a passive device with at least one copper pillar configured to provide an electrical interconnection.

14. The electronic device as recited in claim 9, wherein the passive device includes a passive device that is electrically connected with the integrated circuit chip device.

15. A process comprising:

processing a segmented semiconductor wafer section configured to function as a base layer;

placing an integrated circuit chip device on the segmented semiconductor wafer section, where the integrated circuit chip device includes at least one pillar configured to provide an electrical interconnection to the integrated circuit chip device;

placing a passive device on the segmented semiconductor wafer section and proximate to the integrated circuit chip device;

forming an encapsulation layer over the segmented semiconductor wafer section, the integrated circuit chip device, and the passive device;

facegrinding the encapsulation layer to at least partially expose the electrical interconnection;

forming a redistribution layer structure on the encapsulation layer, where the redistribution layer is electrically coupled to the electrical interconnection; and

forming at least one solder bump on the redistribution layer structure, the at least one solder bump disposed on a surface of the encapsulation layer distal from the segmented semiconductor wafer section.

16. The process as recited in claim 15, wherein processing the segmented semiconductor wafer section includes processing a silicon wafer.

17. The process as recited in claim 15, wherein the at least one pillar includes at least one copper pillar.

18. The process as recited in claim 15, wherein forming the encapsulation layer includes forming an epoxy overmold.

19. The process as recited in claim 15, wherein placing the passive device includes placing the passive device with at least one copper pillar configured to provide an electrical interconnection.

20. The process as recited in claim 15, wherein placing the passive device includes placing a passive device that is electrically connected with the integrated circuit chip device.