System and method of shared bit line MRAM

• US 9,324,768 B1
• Filed: 12/03/2014
• Issued: 04/26/2016
• Est. Priority Date: 12/03/2014
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Zhu, Xiaochun, Li, Xia, Kang, Seung Hyuk
• Primary Examiner(s): Le, Thong Q
• Application Number:
  US14/559,528
• Time in Patent Office: 510 Days
• Field of Search: 365/148, 365/163, 365/222, 365/158, 365/171, 365/189.011, 365/189.07, 365/189.15, 365/189.16, 365/194, 365/225.5, 365/243.5
• US Class Current: 1/1
• CPC Class Codes: G11C 11/16 using elements in which the storage effect is based on magnetic spin effect
• CPC Class Codes: G11C 11/161 details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
• CPC Class Codes: G11C 11/1655 Bit-line or column circuits
• CPC Class Codes: G11C 11/1659 Cell access
• CPC Class Codes: G11C 2213/82 Array having, for accessing a cell, a word line, a bit line and a plate or source line receiving different potentials
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out
• CPC Class Codes: H10B 61/00 Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
• CPC Class Codes: H10B 61/22 of the field-effect transistor [FET] type

Abstract

An STT magnetic memory includes adjacent columns of STT magnetic memory elements having a top electrode and a bottom electrode. A shared bit line is coupled to the top electrode of the STT magnetic memory elements in at least two of the adjacent columns. The bottom electrodes of the STT magnetic memory elements of one of the adjacent columns are selectively coupled to one source line, and the bottom electrodes of the STT magnetic memory elements of another among the adjacent columns are selectively coupled to another source line.

Claims

1. A spin-transfer torque (STT) magnetic memory, comprising:

a plurality of columns of STT magnetic memory elements, wherein the STT magnetic memory elements comprise a top electrode and a bottom electrode;

a plurality of shared bit lines, overlaying the plurality of columns of STT magnetic memory elements, wherein at least one of the plurality of shared bit lines is coupled to the top electrode of the STT magnetic memory elements of a group of at least two of the plurality of columns of STT magnetic memory elements; and

a plurality of source lines, each of the plurality of source lines switchably coupled to the bottom electrode of a STT magnetic memory element of a corresponding one of the plurality of columns of STT magnetic memory elements.

2. The STT magnetic memory of claim 1, wherein the plurality of shared bit lines are configured in an upper metallization layer.

3. The STT magnetic memory of claim 1, wherein the group of at least two of the plurality of columns of STT magnetic memory elements comprises a first group of at least two of the plurality of columns of STT magnetic memory elements, wherein a first shared bit line of the plurality of shared bit lines is coupled to the top electrode of the STT magnetic memory elements of the first group of at least two of the columns of STT magnetic memory elements, and wherein a second shared bit line of the plurality of shared bit lines is coupled to the top electrode of the STT magnetic memory elements of a second group of at least two of the plurality of columns of STT magnetic memory elements.

4. The STT magnetic memory of claim 3, wherein the first group of at least two of the plurality of columns of STT magnetic memory elements comprises at least two adjacent columns of STT magnetic memory elements among the plurality of columns of STT magnetic memory elements, and wherein the second group of at least two of the plurality of columns of STT magnetic memory elements comprises another at least two adjacent columns of STT magnetic memory elements among the plurality of columns of STT magnetic memory elements.

5. The STT magnetic memory of claim 4, wherein the first group of at least two of the plurality of columns of STT magnetic memory elements is adjacent the second group of at least two of the plurality of columns of STT magnetic memory elements.

6. The STT magnetic memory of claim 5, wherein the at least two adjacent columns of STT magnetic memory elements are spaced apart by a center-to-center column pitch, wherein the another at least two adjacent columns of STT magnetic memory elements are spaced apart by said center-to-center column pitch, and wherein the first shared bit line is spaced from the second shared bit line by a shared bit line pitch that is greater than the center-to-center column pitch.

7. The STT magnetic memory of claim 1, wherein each shared bit line of at least a sub-plurality of the plurality of shared bit lines is coupled to the top electrode of the STT magnetic memory elements of a corresponding different group of at least R adjacent columns of STT magnetic memory elements among the plurality of columns of STT magnetic memory elements, wherein R is an integer greater than one.

8. The STT magnetic memory of claim 7, wherein each shared bit line of at least the sub-plurality of the plurality of shared bit lines extends above at least R adjacent ones of the plurality of columns of STT magnetic memory elements.

9. The STT magnetic memory of claim 8, wherein the at least R adjacent ones of the plurality of columns of STT magnetic memory elements, or the another at least R adjacent ones of the plurality of columns of STT magnetic memory elements, or both, are spaced apart by a center-to-center column pitch, wherein at least two of the plurality of shared bit lines extend adjacent to one another and spaced apart by a shared bit line pitch, and wherein the shared bit line pitch is greater than the center-to-center column pitch.

10. The STT magnetic memory of claim 9, wherein R is two, and wherein the center-to-center column pitch is approximately one-half the shared bit line pitch.

11. The STT magnetic memory of claim 9, wherein R is four, and wherein the center-to-center column pitch is approximately one-fourth the shared bit line pitch.

12. The STT magnetic memory of claim 1, wherein the top electrode of the STT magnetic memory elements of at least two adjacent ones of the plurality of columns of STT magnetic memory elements are coupled to a corresponding one of the plurality of shared bit lines.

13. The STT magnetic memory of claim 12, wherein the corresponding one of the plurality of shared bit lines extends above and parallel the at least two adjacent ones of the plurality of columns of STT magnetic memory elements.

14. The STT magnetic memory of claim 12, wherein the corresponding one of the plurality of shared bit lines comprises a metal conductor that extends parallel to and at least partially overlays the at least two adjacent columns of STT magnetic memory elements.

15. The STT magnetic memory of claim 1, wherein a first shared bit line of the plurality of shared bit lines is coupled to the top electrode of the STT magnetic memory elements of a first group of at least four adjacent columns of STT magnetic memory elements, and wherein a second shared bit line of the plurality of shared bit lines is coupled to the top electrode of the STT magnetic memory elements of a second group of at least four adjacent columns of STT magnetic memory elements.

16. The STT magnetic memory of claim 1, wherein the plurality of columns of STT magnetic memory elements, the plurality of shared bit lines, and the plurality of source lines are integrated in at least one semiconductor die.

17. The STT magnetic memory of claim 1, further comprising a device, selected from the group consisting of a set top box, music player, video player, entertainment unit, navigation device, communication device, personal digital assistant (PDA), fixed location data unit, and a computer, into which the plurality of columns of STT magnetic memory elements, the plurality of shared bit lines, and the plurality of source lines are integrated.

18. A method for individually accessing a Spin Transfer Torque (STT) magnetic memory element among a plurality of STT magnetic memory elements coupled to a shared bit line, comprising:

concurrently coupling, to an access voltage, a top electrode of each of a plurality of STT magnetic memory elements in a first column of STT magnetic memory elements and a top electrode of each of a plurality of STT magnetic memory elements in a second column of STT magnetic memory elements; and

selectively coupling, to a complementary access voltage, a bottom electrode of a selected STT magnetic memory element in the first column of STT magnetic memory elements and a bottom electrode of a selected STT magnetic memory element in the second column of STT magnetic memory elements.

19. The method of claim 18, wherein concurrently coupling, to the access voltage, the top electrode of each of the plurality of STT magnetic memory elements in the first column of STT magnetic memory elements and the top electrode of each of the plurality of STT magnetic memory elements in the second column of STT magnetic memory elements comprises applying the access voltage to a shared bit line concurrently coupled to the top electrode of each of the plurality of STT magnetic memory elements in the first column of STT magnetic memory elements and the top electrode of each of the plurality of STT magnetic memory elements in the second column of STT magnetic memory elements.

20. The method of claim 19, wherein selectively coupling, to the complementary access voltage, the bottom electrode of the selected STT magnetic memory element in the first column of STT magnetic memory elements and the bottom electrode of the selected STT magnetic memory element in the second column of STT magnetic memory elements comprises:

coupling the bottom electrode of the STT magnetic memory element in the first column of STT magnetic memory elements to a first source line;

coupling the bottom electrode of the STT magnetic memory element in the second column of STT magnetic memory elements to a second source line; and

selecting among the first source line and the second source line as an enabled source line, and coupling the enabled source line to the complementary access voltage.

21. An apparatus for individually accessing a Spin Transfer Torque (STT) magnetic memory element among at least two adjacent columns of STT magnetic memory elements, comprising:

means for concurrently coupling, to an access voltage, a top electrode of each of a plurality of STT magnetic memory elements in a first column of the at least two adjacent columns of STT magnetic memory elements and a second column of the at least two adjacent columns of STT magnetic memory elements; and

means for selectively coupling, to a complementary access voltage, a bottom electrode of a selected STT magnetic memory element in the first column of the at least two adjacent columns of STT magnetic memory elements and a bottom electrode of a selected STT magnetic memory element in the second column of the at least two adjacent columns of STT magnetic memory elements.

22. The apparatus for individually accessing the STT magnetic memory element among at least two adjacent columns of claim 21, wherein the at least two adjacent columns of STT magnetic memory elements are integrated in at least one semiconductor die.

23. The apparatus for individually accessing the STT magnetic memory element among at least two adjacent columns of claim 21, further comprising a device, selected from the group consisting of a set top box, music player, video player, entertainment unit, navigation device, communication device, personal digital assistant (PDA), fixed location data unit, and a computer, into which the at least two adjacent columns of STT magnetic memory elements are integrated.

24. A Spin Transfer Torque (STT) magnetic memory, comprising:

a group of at least R adjacent columns of STT magnetic memory elements, each of the STT magnetic memory elements comprising a first read/write current terminal and a second read/write current terminal;

a shared bit line, wherein the shared bit line is coupled to the first read/write current terminal of the STT magnetic memory elements in the group of at least R adjacent columns of STT magnetic memory elements;

a first source line, coupled through a first plurality of selectively enabled switch transistors, to the second read/write current terminal of each of a respective first plurality of STT magnetic memory elements in a first column of STT magnetic memory elements in the group of at least R adjacent columns of STT magnetic memory elements; and

a second source line, coupled through a second plurality of selectively enabled switch transistors, to the second read/write current terminal of each of a respective second plurality of STT magnetic memory elements in a second column of STT magnetic memory elements in the group of at least R adjacent columns of STT magnetic memory elements.

25. The STT magnetic memory of claim 24, wherein the shared bit line extends parallel to and at least partially overlays at least two of the at least R adjacent columns of STT magnetic memory elements in the group of at least R adjacent columns of STT magnetic memory elements.

26. The STT magnetic memory of claim 24, wherein the group of at least R adjacent columns of STT magnetic memory elements is a first group of at least R adjacent columns of STT magnetic memory elements, and wherein the shared bit line is a first shared bit line, wherein the STT magnetic memory further comprises:

a second group of at least R adjacent columns of STT magnetic memory elements;

a second shared bit line, wherein the second shared bit line is coupled to the respective first read/write current terminal of the STT magnetic memory elements in the second group of at least R adjacent columns of STT magnetic memory elements;

a third source line, coupled through a third plurality of selectively enabled switch transistors, to the second read/write current terminal of each of a respective third plurality of STT magnetic memory elements in a first column of STT magnetic memory elements in the second group of at least R adjacent columns of STT magnetic memory elements; and

a fourth source line, coupled through a fourth plurality of selectively enabled switch transistors, to the second read/write current terminal of each of a respective second plurality of STT magnetic memory elements in a second column of STT magnetic memory elements in the second group of at least R adjacent columns of STT magnetic memory elements.

27. The STT magnetic memory of claim 26, wherein R is two.

28. The STT magnetic memory of claim 26, wherein R is four.

29. The STT magnetic memory of claim 24, wherein the group of at least R adjacent columns of STT magnetic memory elements, the shared bit line, the first source line, and the second source line are integrated in at least one semiconductor die.

30. The STT magnetic memory of claim 29, further comprising a device, selected from the group consisting of a set top box, music player, video player, entertainment unit, navigation device, communication device, personal digital assistant (PDA), fixed location data unit, and a computer, into which the group of at least R adjacent columns of STT magnetic memory elements, the shared bit line, the first source line, and the second source line are integrated.