Bidirectional MOSFET with suppressed bipolar snapback and method of manufacture

• US 9,324,800 B1
• Filed: 02/11/2015
• Issued: 04/26/2016
• Est. Priority Date: 02/11/2015
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Ku, Pon Sung, Qin, Ganming, Zitouni, Moaniss, Zupac, Dragan, De Frsart, Edouard D.
• Primary Examiner(s): Schoenholtz, Joseph
• Application Number:
  US14/619,232
• Time in Patent Office: 440 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/086 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A bidirectional trench FET device includes a semiconductor substrate, a trench in the substrate extending vertically from the surface of the substrate, and a body region laterally adjacent the trench. A source region is disposed in the semiconductor substrate between the body region and the surface of the substrate. A dielectric layer is disposed over the surface and a body electrode is disposed over the dielectric layer. A body contact plug extends through the dielectric layer to interconnect the body region with the body electrode, and the body contact plug is electrically isolated from the source region. Two separate metal layers are implemented to make multiple body and source contacts electrically isolated from one another throughout the active area of the device. The low resistive path by the body contact plug and the separate metal layers enables suppression of bipolar snapback without losing bidirectional switching capability.

Claims

1. A bidirectional trench field effect transistor (FET) device comprising:

a semiconductor substrate having a surface;

a trench in said semiconductor substrate extending vertically from said surface;

a body region disposed in said semiconductor substrate and laterally adjacent to said trench, said body region being spaced from said surface and having a first conductivity type;

a source region disposed at said surface of said semiconductor substrate between said body region and said surface;

a dielectric layer disposed over said surface of said semiconductor substrate;

a body electrode disposed over said dielectric layer; and

a body contact plug extending through said dielectric layer, said body contact plug interconnecting said body region with said body electrode, and said body contact plug being electrically isolated from said source region.

2. The bidirectional trench FET device of claim 1 wherein said body contact plug further extends through said source region, and said bidirectional trench FET further comprises a dielectric lining surrounding said body contact plug extending through said source region to electrically isolate said body contact plug from said source region.

3. The bidirectional trench FET device of claim 1 further comprising a drift region disposed in said semiconductor substrate between said body region and said source region, said drift region having a second conductivity type, wherein said body contact plug additionally extends through said drift region to interconnect said body region with said body electrode.

4. The bidirectional trench FET device of claim 1 further comprising a dopant region disposed between said body contact plug and said body region.

5. The bidirectional trench FET device of claim 4 wherein said body region comprises a P-region, said body contact plug extends to said body region, and said dopant region comprises a P+ region.

6. The bidirectional trench FET device of claim 1 wherein:

said body region comprises a P-region; and

said bidirectional trench FET device further comprises a P-link region disposed in said semiconductor substrate between said body region and said surface of said semiconductor substrate, said P-link region being electrically isolated from said source region and said body contact plug extending to said P-link region.

7. The bidirectional trench FET device of claim 1 wherein said dielectric layer is a first dielectric layer, and said bidirectional trench FET device further comprises:

a source electrode vertically disposed away from said body electrode; and

a source interconnect interconnecting said source region with said source electrode, wherein said source electrode and said source interconnect are electrically isolated from said body electrode.

8. The bidirectional trench FE|T device of claim 7 wherein said source interconnect is electrically isolated from said body contact plug.

9. The bidirectional trench FET device of claim 1 wherein said body contact plug comprises a tungsten contact plug.

10. The bidirectional trench FET device of claim 1 wherein said body contact plug comprises a polysilicon contact plug.

11. The bidirectional trench FET device of claim 1 wherein said body contact plug comprises a doped polysilicon contact plug.

12. A bidirectional trench field effect transistor (FET) device comprising:

a semiconductor substrate having a surface;

a trench in said semiconductor substrate extending vertically from said surface;

a body region disposed in said semiconductor substrate and laterally adjacent to said trench, said body region being spaced from said surface and having a first conductivity type;

a source region disposed at said surface of said semiconductor substrate between said body region and said surface;

a dielectric layer disposed over said surface of said semiconductor substrate;

a body electrode disposed over said dielectric layer;

a body contact plug extending through said dielectric layer and said source region, said body contact plug interconnecting said body region with said body electrode;

a dielectric lining surrounding said body contact plug, said dielectric lining electrically isolating said body contact plug from said source region;

a source electrode vertically disposed away from said body electrode; and

a source interconnect interconnecting said source region with said source electrode, wherein said source electrode and said source interconnect are electrically isolated from said body electrode.

13. The bidirectional trench FET device of claim 12 wherein said source interconnect is electrically isolated from said body contact plug.

14. The bidirectional trench FET device of claim 12 further comprising a dopant region disposed between said body contact plug and said body region, said dopant region being electrically isolated from said source region via said dielectric lining.

15. The bidirectional trench FET device of claim 14 wherein said body region comprises a P-region, said body contact plug extends to said body region, and said dopant region comprises a P+ region.

16. The bidirectional trench FET device of claim 12 wherein:

said body region comprises a P-region; and

said bidirectional trench FET device further comprises a P-link region disposed in said semiconductor substrate between said body region and said surface of said semiconductor substrate, said P-link region being electrically isolated from said source region, wherein said body contact plug extends to said P-link region.

17. A method of fabricating a bidirectional trench field effect transistor (FET) device having suppressed bipolar snapback, said bidirectional trench FET including a semiconductor substrate having a surface, a trench in said semiconductor substrate extending vertically from said surface, a body region disposed in said semiconductor substrate and laterally adjacent to said trench, said body region being spaced from said surface and having a first conductivity type, and a source region disposed at said surface of said semiconductor substrate between said body region and said surface, and said method comprising:

disposing a dielectric layer over said surface of said semiconductor substrate;

disposing a body electrode over said dielectric layer;

forming a body contact plug extending through said dielectric layer to interconnect said body region with said body electrode; and

electrically isolating said body contact plug from said source region.

18. The method of claim 17 wherein a drift region is interposed between said body region and said source region, and said method further comprises:

prior to said disposing said dielectric layer, etching an opening extending from said surface of said semiconductor substrate through said source region, said drift region, and said body region, wherein said disposing said dielectric layer fills said opening with said dielectric layer;

removing a portion of said dielectric layer within said opening to expose said body region while concurrently leaving a remaining portion of said dielectric layer intact on sidewalls of said opening, said removing producing a second opening surrounded by said remaining portion of said dielectric layer; and

said forming said body contact plug includes depositing a plug material in said second opening, said remaining portion of said dielectric layer forming a dielectric lining surrounding said body contact plug and electrically isolating said body contact plug from said source region.

19. The method of claim 18 further comprising implanting a dopant region between said body contact plug and said body region, said dopant region being electrically isolated from said source region via said dielectric lining, wherein said body region comprises a P-region and said dopant region comprises a P+ region.

20. The method of claim 17 further comprising wherein said dielectric layer is a first dielectric layer, and said method further comprises:

disposing a second dielectric layer over said body electrode and said source region;

disposing a source electrode over said second dielectric layer, wherein said second dielectric layer electrically isolates said body electrode from said source electrode; and

forming a source interconnect extending through said second dielectric layer and interconnecting said source region with said source electrode, wherein said source interconnect is electrically isolated from said body contact plug.