Structures and devices including a tensile-stressed silicon arsenic layer and methods of forming same

• US 9,324,811 B2
• Filed: 09/04/2013
• Issued: 04/26/2016
• Est. Priority Date: 09/26/2012
• Status: Active Grant

• Current Assignee: ASM IP Holding B.V. (ASM International NV)
• Original Assignee: ASM IP Holding B.V. (ASM International NV)
• Inventors: Weeks, Keith Doran
• Primary Examiner(s): Gebreyesus, Yosef
• Application Number:
  US14/018,345
• Publication Number:
  US 20140084341A1
• Time in Patent Office: 965 Days
• Field of Search: 438/478, 438/50, 438/218, 438/301, 438/658, 438/210, 438/300, 257/190
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02521 Materials
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02576 N-type
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 21/67207 comprising a chamber adapted to a particular process
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/267 in different semiconductor regions , e.g. heterojunctions H01L29/263 takes precedence
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate

Abstract

Structures including a tensile-stressed silicon arsenic layer, devices including the structures, and methods of forming the devices and structures are disclosed. Exemplary tensile-stressed silicon arsenic layer have an arsenic doping level of greater than 5 E+20 arsenic atoms per cubic centimeter. The structures can be used to form metal oxide semiconductor devices.

Claims

1. A method of forming a tensile-stressed silicon arsenic layer, the method comprising the steps of:

supporting a substrate comprising silicon in a reactor, wherein a surface of the substrate is exposed to a reaction region within the reactor;

supplying a silicon source to the reactor;

supplying an arsenic source to the reactor; and

at a pressure between about 90 Torr and about 300 Torr, forming the tensile-stressed silicon arsenic layer having a concentration of arsenic of greater than 1 E+21 arsenic atoms/cubic centimeter on the surface.

2. The method of forming a tensile-stressed silicon arsenic layer of claim 1, wherein during the step of forming the tensile-stressed silicon arsenic layer, a temperature of the reaction region is between 500°

C. and 700°

C.

3. The method of forming a tensile-stressed silicon arsenic layer of claim 1, wherein during the step of forming the tensile-stressed silicon arsenic layer, a pressure within the reaction region is between 90 and 300 Torr.

4. The method of forming a tensile-stressed silicon arsenic layer of claim 1, wherein during the step of forming the tensile-stressed silicon arsenic layer, a carrier gas flow rate is between about 10 to about 40 standard liters per minute.

5. The method of forming a tensile-stressed silicon arsenic layer of claim 1, wherein during the step of supplying an arsenic source to the reactor, arsenic is provided in a non-reactive diluent.

6. The method of forming a tensile-stressed silicon arsenic layer of claim 1, wherein the step of forming the tensile-stressed silicon arsenic layer comprises epitaxially forming the tensile-stressed silicon arsenic layer on the silicon surface.

7. The method of forming a tensile-stressed silicon arsenic layer of claim 1, wherein the step of forming the tensile-stressed silicon arsenic layer comprises forming a layer comprising greater than or equal to 5 E+21 arsenic atoms/cubic centimeter.

8. The method of forming a tensile-stressed silicon arsenic layer of claim 1, further comprising forming a structure comprising the tensile-stressed silicon arsenic layer.

9. The method of forming a tensile-stressed silicon arsenic layer of claim 1, further comprising forming a device comprising the tensile-stressed silicon arsenic layer.

10. The method of claim 1, wherein the tensile-stressed silicon arsenic layer forms a channel region of a transistor device.