Semiconductor device including nanowire transistor

• US 9,324,812 B2
• Filed: 09/17/2014
• Issued: 04/26/2016
• Est. Priority Date: 10/02/2013
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Yang, Jung-Gil, Kim, Sang-Su, Hur, Sung-Gi
• Primary Examiner(s): Dang, Trung Q
• Application Number:
  US14/489,418
• Publication Number:
  US 20150090958A1
• Time in Patent Office: 587 Days
• Field of Search: 257/27
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02233 of the semiconductor substrate or a semiconductor layer
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/0642 Isolation within the component, i.e. internal isolation
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/0676 oriented perpendicular or at an angle to a substrate
• CPC Class Codes: H01L 29/068 comprising a junction
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/16 including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/161 including two or more of the elements provided for in group H01L29/16 , e.g. alloys H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/20 including, apart from doping materials or other impurities, only AIIIBV compounds
• CPC Class Codes: H01L 29/267 in different semiconductor regions , e.g. heterojunctions H01L29/263 takes precedence
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/785 : having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78684 : having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys H01L29/7869 takes precedence
• CPC Class Codes: H01L 29/78696 : characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A semiconductor device includes at least one nanowire that is disposed over a substrate, extends to be spaced apart from the substrate, and includes a channel region, a gate that surrounds at least a part of the channel region, and a gate dielectric film that is disposed between the channel region and the gate. A source/drain region that contacts one end of the at least one nanowire is formed in a semiconductor layer that extends from the substrate to the one end of the at least one nanowire. Insulating spacers are formed between the substrate and the at least one nanowire. The insulating spacers are disposed between the gate and the source/drain region and are formed of a material that is different from a material of the gate dielectric film.

Claims

1. A semiconductor device comprising:

at least one nanowire that is disposed over a substrate, extends to be spaced apart from the substrate, and comprises a channel region;

a gate that surrounds at least a part of the channel region;

a gate dielectric film that is disposed between the channel region and the gate;

a semiconductor layer that extends from the substrate to one end of the at least one nanowire, and comprises a source/drain region that contacts the one end of the at least one nanowire;

insulating spacers that are disposed between the gate and the source/drain region and between the substrate and the at least one nanowire, and are formed of a material that is different from a material of the gate dielectric film; and

a buffer layer that is disposed in a first region of the substrate and between the substrate and the gate,

wherein the buffer layer is formed of a material that has a lattice constant that is higher than a lattice constant of the substrate.

2. The semiconductor device of claim 1, wherein the gate dielectric film is disposed between the gate and the insulating spacers.

3. The semiconductor device of claim 1, wherein the insulating spacers are formed of a first material that has a first dielectric constant, and the gate dielectric film is formed of a second material that has a second dielectric constant higher than the first dielectric constant.

4. The semiconductor device of claim 1, wherein the at least one nanowire is formed of a group IV semiconductor, a group IV-IV compound semiconductor, or a group III-V compound semiconductor.

5. The semiconductor device of claim 4, wherein the group III-V compound semiconductor is formed of InGaAs, InAs, GaSb, InSb, or a combination thereof.

6. The semiconductor device of claim 1, wherein the insulating spacers are formed of an oxide of a group IV semiconductor, an oxide of a group IV-IV compound semiconductor, an oxide of a group III-V compound semiconductor, or a silicon oxide.

7. The semiconductor device of claim 1, wherein the semiconductor layer is formed of a SiGe film, a Ge film, a SiC film, or an InGaAs film.

8. The semiconductor device of claim 1, wherein the insulating spacers are first insulating spacers, and further comprising second insulating spacers that are disposed over the at least one nanowire and cover side walls of the gate, and

wherein the first insulating spacers and the second insulating spacers are formed of different materials.

9. The semiconductor device of claim 8, wherein the first insulating spacers and the second insulating spacers are formed at different levels on the substrate to vertically overlap with each other.

10. The semiconductor device of claim 1, wherein the at least one nanowire comprises a plurality of nanowires that have different distances from the substrate, and

wherein the insulating spacers comprise a plurality of insulating spacers that are formed in spaces between the plurality of nanowires.

11. A semiconductor device comprising:

a first transistor that is formed in a first region of a substrate; and

a second transistor that is formed in a second region of the substrate,

wherein the first transistor comprises;

a first nanowire including a first channel region;

a first gate surrounding the first nanowire;

a first gate dielectric film disposed between the first nanowire and the first gate;

a first source/drain region connected to one end of the first nanowire; and

first inner insulating spacers disposed between the first gate dielectric film and the first source/drain region, the first gate dielectric film further disposed between the first source/drain region and the first gate, and

wherein the second transistor comprises;

a second nanowire including a second channel region;

a second gate surrounding the second nanowire;

a second gate dielectric film disposed between the second nanowire and the second gate; and

a second source/drain region connected to one end of the second nanowire and formed of a material different from a material of the first source/drain region.

12. The semiconductor device of claim 11, wherein the second transistor further comprises second inner insulating spacers that are disposed between the second gate dielectric film and the second source/drain region, the second gate dielectric film further disposed between the second source/drain region and the second gate.

13. The semiconductor device of claim 12, wherein at least one of the first inner insulating spacers and the second inner insulating spacers is formed of an oxide of a group IV semiconductor, an oxide of a group IV-IV compound semiconductor, an oxide of a group III-V compound semiconductor, or a silicon oxide.

14. The semiconductor device of claim 11, wherein the first inner insulating spacers and the first gate dielectric film are formed of different materials.

15. A semiconductor device comprising:

at least one nanowire that is disposed over a substrate, extends to be spaced apart from the substrate, and comprises a channel region;

a gate that surrounds at least a part of the channel region;

a gate dielectric film that is disposed between the channel region and the gate;

a semiconductor layer that extends from the substrate to one end of the at least one nanowire, and comprises a source/drain region that contacts the one end of the at least one nanowire;

first insulating spacers that are disposed between the gate and the source/drain region and between the substrate and the at least one nanowire, and are formed of a material that is different from a material of the gate dielectric film;

second insulating spacers that are disposed over the at least one nanowire and cover side walls of the gate, and are formed of a material that is different from a material of the gate dielectric film; and

a buffer layer that is disposed in a first region of the substrate and between the substrate and the gate,

wherein the buffer layer is formed of a material that has a lattice constant that is higher than a lattice constant of the substrate, and

wherein the source/drain region extends to a level higher than a top-most level of the at least one nanowire or a top-most level of any other nanowires formed adjacent to the source/drain region.

16. The semiconductor device of claim 15, wherein the first insulating spacers and the second insulating spacers are formed of different materials.

17. The semiconductor device of claim 15, wherein the first insulating spacers and the second insulating spacers are formed at different levels on the substrate to vertically overlap with each other.

18. The semiconductor device of claim 15, wherein the second insulating spacers surround a portion of the at least one nanowire and a portion of the first insulating spacers.

19. The semiconductor device of claim 15, wherein the gate dielectric film is disposed between the gate and the first and second insulating spacers.