Trench-gated MIS devices

• US 9,324,858 B2
• Filed: 11/01/2010
• Issued: 04/26/2016
• Est. Priority Date: 03/22/2002
• Status: Expired due to Term

• Current Assignee: Vishay Siliconix
• Original Assignee: Vishay Siliconix
• Inventors: Bhalla, Anup, Pitzer, Dorman, Korec, Jacek, Shi, Xiaorong, Lui, Sik
• Primary Examiner(s): Diaz, Jose R
• Application Number:
  US12/917,378
• Publication Number:
  US 20110042742A1
• Time in Patent Office: 2,003 Days
• Field of Search: 257330-334, 257/202
• US Class Current: 1/1
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/0661 specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42372 characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out H01L29/42324 takes precedence
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7803 structurally associated with at least one other device assemblies H01L25/00; integrated circuits H01L27/00
• CPC Class Codes: H01L 29/7804 the other device being a pn-junction diode
• CPC Class Codes: H01L 29/7806 the other device being a Schottky barrier diode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/8725 of the trench MOS barrier type [TMBS]
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: Y10S 257/905 Plural dram cells share common contact or common trench

Abstract

In a trench-gated MIS device contact is made to the gate within the trench, thereby eliminating the need to have the gate material, typically polysilicon, extend outside of the trench. This avoids the problem of stress at the upper corners of the trench. Contact between the gate metal and the polysilicon is normally made in a gate metal region that is outside the active region of the device. Various configurations for making the contact between the gate metal and the polysilicon are described, including embodiments wherein the trench is widened in the area of contact. Since the polysilicon is etched back below the top surface of the silicon throughout the device, there is normally no need for a polysilicon mask, thereby saving fabrication costs.

Claims

1. A trench-gated MIS device in a semiconductor chip and comprising:

a first active area including transistor cells;

a second active area including transistor cells;

a gate metal area including no transistor cells, wherein the first and second active areas are located on opposite sides of the gate metal area;

a gate metal layer overlying the gate metal area; and

a plurality of trenches formed in a pattern on a surface of the semiconductor chip, wherein the plurality of trenches extend from the first active area to the second active area and pass through the gate metal area.

2. The trench-gated MIS device of claim 1, wherein the plurality of trenches include:

walls lined with a layer of an insulating material, and

a conductive gate material disposed in the trenches, wherein a top surface of the conductive gate material is at a level below a top surface of the semiconductor chip;

and further comprising a nonconductive layer overlying the active and gate metal areas, and the gate metal layer overlying the nonconductive layer in the gate metal area.

3. The trench-gated MIS device of claim 1, wherein the plurality of trenches have walls lined with a layer of an insulating material, a conductive gate material being disposed in the trenches, a top surface of the conductive gate material being at a level below a top surface of the semiconductor chip, a nonconductive layer overlying the active and gate metal areas, and the gate metal layer overlying the nonconductive layer in the gate metal area, and wherein the plurality of trenches are first gate fingers.

4. The trench-gated MIS device of claim 3, wherein at least one of the first gate fingers from the first active area contains a first widened portion in the gate metal area and at least one of the first gate fingers from the second active area contains a second widened portion in the gate metal area.

5. The trench-gated MIS device of claim 4, further comprising:

a first aperture formed in the nonconductive layer over the first widened portion in the gate metal area, wherein the first aperture is filled with the gate metal layer such that the gate metal layer contacts the conductive gate material.

6. The trench-gated MIS device of claim 5, further comprising:

a second aperture formed in the nonconductive layer over the second widened portion in the gate metal area, wherein the second aperture is filled with the gate metal layer such that the gate metal layer contacts the conductive gate material.

7. The trench-gated MIS device of claim 6, wherein the first and second widened portions are offset with respect to each other in a direction parallel to the first gate fingers.

8. A trench-gated MIS device in a semiconductor chip and comprising:

a first active area including transistor cells;

a second active area including transistor cells;

a gate metal area including no transistor cells, wherein the first and second active areas are located on opposite sides of the gate metal area;

a gate metal layer overlying the gate metal area; and

a plurality of trenches extending from the first active area to the second active area and passing through the gate metal area.

9. The trench-gated MIS device of claim 8, wherein the plurality of trenches include walls lined with a layer of an insulating material and a conductive gate material disposed in the trenches, wherein a top surface of the conductive gate material is at a level below a top surface of the semiconductor chip.

10. The trench-gated MIS device of claim 9, further comprising a nonconductive layer overlying the active and gate metal areas, and the gate metal layer overlying the nonconductive layer in the gate metal area.

11. A trench-gated MIS device in a semiconductor chip and comprising:

a first active area including transistor cells;

a second active area including transistor cells;

a gate metal area including no transistor cells, wherein the first and second active areas are located on opposite sides of the gate metal area;

a gate metal layer overlying the gate metal area,

a first plurality of trenches and a second plurality of trenches formed in a pattern on a surface of the semiconductor chip, wherein the first plurality of trenches extend from the first active area into the gate metal area, wherein the second plurality of trenches extend from the second active area into the gate metal area; and

a trench formed in the gate metal area, wherein the first plurality and the second plurality of trenches are first gate fingers, wherein the trench in the gate metal area is a second gate finger, and wherein the second gate finger intersects a plurality of the first gate fingers and is perpendicular to the plurality of first gate fingers.

12. The trench-gated MIS device of claim 11, wherein the first plurality and second plurality of trenches have walls lined with a layer of an insulating material, a conductive gate material being disposed in the trenches, a top surface of the conductive gate material being at a level below a top surface of the semiconductor chip, a nonconductive layer overlying the active and gate metal areas, and the gate metal layer overlying the nonconductive layer in the gate metal area,

wherein the trench in the gate metal area has walls lined with the layer of the insulating material, and wherein the conductive gate material is disposed in the trench in the gate metal area.

13. The trench-gated MIS device of claim 12, wherein the gate metal layer extends longitudinally in a direction perpendicular to a direction of the first plurality and the second plurality of trenches in the gate metal area.

14. The trench-gated MIS device of claim 12, wherein a width of the second gate finger is greater than a width of the first gate fingers, and further comprising:

an aperture formed in the nonconductive layer over the second gate finger in the gate metal area, wherein the aperture is filled with the gate metal layer such that the gate metal layer contacts the conductive gate material.

15. The trench-gated MIS device of claim 12, further comprising a plurality of apertures formed in the nonconductive layer over portions of the second gate finger in the gate metal area, wherein the portions do not extend into an intersection between the first gate fingers and the second gate finger, wherein the apertures are filled with the gate metal layer such that the gate metal layer contacts the conductive gate material.

16. The trench-gated MIS device of claim 15, wherein a width of the portions of the second gate finger is greater than a width of the first gate fingers in the gate metal area.

17. The trench-gated MIS device of claim 12, wherein the first gate fingers end at the second gate finger so as to form T intersections, and further comprising:

an aperture formed in the nonconductive layer over the second gate finger in the gate metal area, wherein the aperture is filled with the gate metal layer such that the gate metal layer contacts the conductive gate material.

18. The trench-gated MIS device of claim 17, wherein a width of the second gate finger is greater than a width of the first gate fingers.

19. The trench-gated MIS device of claim 18, wherein at least one of the first gate fingers extends from the first active area, and wherein at least one of the first gate fingers extends from the second active area.

20. The trench-gated MIS device of claim 19 of the first gate fingers from the first active area and the at least one of the first gate fingers from the second active area are located on opposite sides of the second gate finger.