Data rate and PVT adaptation with programmable bias control in a SerDes receiver

• US 9,325,546 B1
• Filed: 11/14/2014
• Issued: 04/26/2016
• Est. Priority Date: 11/14/2014
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Inventors: Mobin, Mohammad S., Mao, Weiwei, Hardy, Brett D.
• Primary Examiner(s): Bayard, Emmanuel
• Application Number:
  US14/541,345
• Publication Number:
  US 20160142233A1
• Time in Patent Office: 529 Days
• Field of Search: 375232-234, 375/350
• US Class Current: 1/1
• CPC Class Codes: H03G 3/3078 Circuits generating control signals for digitally modulated signals
• CPC Class Codes: H04L 25/0298 Arrangement for terminating transmission lines
• CPC Class Codes: H04L 25/03878 Line equalisers; line build-out devices
• CPC Class Codes: H04L 7/0079 Receiver details

Abstract

Described embodiments provide for, in a SerDes device, an adaptation process that adjusts data path gain through programmable-bias based on process, voltage, temperature (PVT) and data rate changes. Such adaptation process extends bias current dynamic range, and low frequency gain can be programmed to a desired target range of values for a given variable gain amplifier (VGA) setting at any PVT and data rate corner. A receive (RX) data path structure auto-adapts data path gain through programmable bias based on sensed PVT and data rate changes. The low frequency attenuation/gain range is extended, and can be programmed to a desirable targeted range by a SerDes device RX adaptive process for a given VGA and linear equalizer (LEQ) setting at any given PVT and data rate condition.

Claims

1. A method of setting bias of a receive data path in a receiver device, the method comprising:

initializing, by bias adjustment circuitry, bias settings of at least one of a variable gain amplifier (VGA), a linear equalizer (LEQ), a multiplexer (MUX) and a combiner of the receive data path to initial bias settings;

detecting a data rate of incoming data of the receive data path;

measuring, with corresponding sensors, at least one of a present process, temperature and voltage level for the receive data path; and

associating, by bias adaptation control logic, a combination of the detected data rate and the at least one measured present process, temperature and voltage level for the receive data path with corresponding bias settings for boost and for gain or attenuation in the receive data path; and

adjusting the bias of the at least one of the variable gain amplifier (VGA), the linear equalizer (LEQ), the multiplexer (MUX) and the combiner of the receive data path based on the associated corresponding bias settings for boost and for gain or attenuation that were associated with the combination of the detected data rate and the at least one of measured present process, temperature, and voltage level for the receive data path.

2. The method of claim 1, wherein, the associating including accessing a look-up table in memory having a table of bias settings for boost and for gain or attenuation in the receive data path, wherein entries of the table are addressed via corresponding data rate, process, voltage and temperature levels.

3. The method of claim 1, comprising repeating the measuring, associating and adjusting until the receive data path reaches a steady state condition.

4. The method of claim 3, wherein the repeating includes receiving at least one present data eye margin value, and comparing the present data eye margin value to a threshold to determine the steady state condition.

5. The method of claim 4, wherein the present data eye margin value includes at least one of a horizontal and a vertical margin.

6. The method of claim 1, wherein the adjusting, by bias control circuitry, the bias of the at least one of the variable gain amplifier (VGA), the linear equalizer (LEQ), the multiplexer (MUX) and the combiner includes enabling or disabling switches of corresponding bias current generators based on the associated corresponding bias settings for boost and for gain or attenuation.

7. The method of claim 1, comprising monitoring the receiver device over changing Process, Voltage and Temperature (PVT) conditions, wherein the method is applied repeatedly over to maintain a relatively steady condition in the receive data path.

8. The method of claim 1, wherein the method is embodied in a Serializer/Deserializer (SerDes) device.

9. Apparatus for setting bias of a receive data path in a receiver device, the apparatus comprising:

bias adjustment circuitry configured to initialize bias settings of at least one of a variable gain amplifier (VGA), a linear equalizer (LEQ), a multiplexer (MUX) and a combiner of the receive data path to initial bias settings;

a data rate detector configured to detect a data rate of incoming data of the receive data path;

sensors configured to measure at least one of a present process, temperature and voltage level for the receive data path; and

bias control adaptation logic configured to associate a combination of the detected data rate and the at least one measured present process, temperature and voltage level for the receive data path with corresponding bias settings for boost and for gain or attenuation in the receive data path; and

wherein the bias control adaptation logic adjusts, via a control signal to the bias adjustment circuitry, the bias of the at least one of the variable gain amplifier (VGA), the linear equalizer (LEQ), the multiplexer (MUX) and the combiner of the receive data path based on the associated corresponding bias settings for boost and for gain or attenuation that were associated with the combination of the detected data rate and the at least one of measured present process, temperature, and voltage level for the receive data path.

10. The apparatus of claim 9, wherein, the bias control adaptation logic accesses a look-up table in memory having a table of bias settings for boost and for gain or attenuation in the receive data path, wherein entries of the table are addressed via corresponding data rate, process, voltage and temperature levels.

11. The apparatus of claim 9, wherein the apparatus repetitively measures, associates and adjusts until the receive data path reaches a steady state condition.

12. The apparatus of claim 11, wherein the bias control adaptation logic receives at least one present data eye margin value, and compares the present data eye margin value to a threshold to determine the steady state condition.

13. The apparatus of claim 11, wherein the bias control circuitry adjusts the bias of the at least one of the variable gain amplifier (VGA), the linear equalizer (LEQ), the multiplexer (MUX) and the combiner by enabling or disabling switches of corresponding bias current generators based on the associated corresponding bias settings for boost and for gain or attenuation.

14. The apparatus of claim 9, wherein the sensors monitor the receiver device over changing Process, Voltage and Temperature (PVT) conditions to maintain a relatively steady condition in the receive data path.

15. The apparatus of claim 9, wherein the apparatus is embodied in a Serializer/Deserializer (SerDes) device.

16. The apparatus of claim 9, wherein the apparatus is embodied in an integrated circuit.

17. A non-transitory machine-readable storage medium, having encoded thereon program code, wherein, when the program code is executed by a machine, the machine implements a method for setting bias of a receive data path in a receiver device, comprising:

initializing, by bias adjustment circuitry, bias settings of at least one of a variable gain amplifier (VGA), a linear equalizer (LEQ), a multiplexer (MUX) and a combiner of the receive data path to initial bias settings;

detecting a data rate of incoming data of the receive data path;

measuring, with corresponding sensors, at least one of a present process, temperature and voltage level for the receive data path; and

associating, by bias adaptation control logic, a combination of the detected data rate and the at least one measured present process, temperature and voltage level for the receive data path with corresponding bias settings for boost and for gain or attenuation in the receive data path; and

adjusting the bias of the at least one of the variable gain amplifier (VGA), the linear equalizer (LEQ), the multiplexer (MUX) and the combiner of the receive data path based on the associated corresponding bias settings for boost and for gain or attenuation.

18. The non-transitory machine-readable storage medium of claim 17, wherein, the associating including accessing a look-up table in memory having a table of bias settings for boost and for gain or attenuation in the receive data path, wherein entries of the table are addressed via corresponding data rate, process, voltage and temperature levels.

19. The non-transitory machine-readable storage medium of claim 17, comprising repeating the measuring, associating and adjusting until the receive data path reaches a steady state condition.

20. The non-transitory machine-readable storage medium of claim 19, wherein the repeating includes receiving at least one present data eye margin value, and comparing the present data eye margin value to a threshold to determine the steady state condition.