Managing high-coherence-miss cache lines in multi-processor computing environments

• US 9,329,890 B2
• Filed: 09/26/2013
• Issued: 05/03/2016
• Est. Priority Date: 09/26/2013
• Status: Active Grant

• Current Assignee: MediaTek, Inc.
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Busaba, Fadi Y., Cain, Harold W. III, Gschwind, Michael K., Michael, Maged M., Salapura, Valentina, Schwarz, Eric M., Shum, Chung-Lung K.
• Primary Examiner(s): Tsai, Henry
• Assistant Examiner(s): Hassan, Aurangzeb
• Application Number:
  US14/037,925
• Publication Number:
  US 20150089154A1
• Time in Patent Office: 950 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G06F 1/1632 External expansion units, e.g. docking stations
• CPC Class Codes: G06F 12/0815 Cache consistency protocols
• CPC Class Codes: G06F 12/0831 using a bus scheme, e.g. with bus monitoring or watching means
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: G06F 2212/1016 Performance improvement
• CPC Class Codes: G06F 2212/502 using adaptive policy
• CPC Class Codes: G06F 3/038 Control and interface arrangements therefor, e.g. drivers or device-embedded control circuitry
• CPC Class Codes: G06F 9/467 Transactional memory G06F9/528 takes precedence

Abstract

Cache lines in a multi-processor computing environment are configurable with a coherency mode. Cache lines in full-line coherency mode are operated or managed with full-line granularity. Cache lines in sub-line coherency mode are operated or managed as sub-cache line portions of a full cache line. A high-coherence-miss cache line may be placed in sub-line coherency mode. A cache line may be associated with a counter in a coherence miss detection table that is incremented whenever an access of the cache line results in a coherence request. The cache line may be a high-coherence-miss cache line when the counter satisfies a high-coherence-miss criterion, such as reaching a threshold value. The cache line may be returned to full-line coherency mode when a reset criterion is satisfied.

Claims

1. A method for cache management in a multi-processor computing environment, the computing environment including a cache configured to hold a plurality of cache lines, each cache line configurable with a coherency mode, the method comprising:

accessing a first cache line in a full-line coherency mode, wherein cache control logic associated with the cache is configured to operate or manage the first cache line in the full-line coherency mode with a full-line granularity, the accessing the first cache line resulting in a coherence request, wherein based on the accessing, incrementing a counter in an entry in a coherence miss detection table, the entry associating the counter with the first cache line;

determining that the first cache line is a high-coherence-miss cache line, wherein the determining that the first cache line is the high-coherence-miss cache line comprises determining that the incremented counter satisfies a high-coherence-miss criterion; and

based on the determining, placing the first cache line in a sub-line coherency mode, wherein the cache control logic is configured to operate or manage a plurality of sub-cache line portions of the first cache line in the sub-line coherency mode.

2. The method of claim 1, further comprising:

receiving, from another requestor in the computing environment, a request for the first cache line, the request targeting a memory address within the first cache line;

selecting a first sub-cache line portion of the first cache line, the first sub-cache line portion associated with the memory address;

notifying the requestor that only a sub-cache line portion of the first cache line will be returned; and

returning to the requestor the first sub-cache line portion in response to the request.

3. The method of claim 1, wherein the first cache line is a first-cache copy of the first cache line in a first cache, and wherein a second-cache copy of the first cache line in a second cache remains in the full-line coherency mode after the placing the first-cache copy in the sub-line coherency mode.

4. The method of claim 1, wherein the entry further associates the counter with at least one cache line adjacent to the first cache line.

5. The method of claim 1, wherein the entry further associates the counter with a hash value of a memory address associated with the first cache line.

6. A computer system for cache management in a multi-processor computing environment, the computing environment including a cache configured to hold a plurality of cache lines, each cache line configurable with a coherency mode, the computer system comprising:

a memory; and

a processor in communication with the memory, wherein the computer system is configured to perform a method, the method comprising;

accessing a first cache linein a full-line coherency mode, wherein cache control logic associated with the cache is configured to operate or manage the first cache line in the full-line coherency mode with a full-line granularity, the accessing the first cache line resulting in a coherence request, wherein based on the accessing, incrementing a counter in an entry in a coherence miss detection table, the entry associating the counter with the first cache line;

determining that the first cache line is a high-coherence-miss cache line, wherein the determining that the first cache line is the high-coherence-miss cache line comprises determining that the incremented counter satisfies a high-coherence-miss criterion; and

based on the determining, placing the first cache line in a sub-line coherency mode, wherein the cache control logic is configured to operate or manage a plurality of sub-cache line portions of the first cache line in the sub-line coherency mode.

7. The computer system of claim 6, wherein the determining that the incremented counter satisfies the high-coherence-miss criterion comprises:

determining that the incremented counter has reached a threshold value.

8. The computer system of claim 6, wherein the determining that the incremented counter satisfies the high-coherence-miss criterion comprises:

calculating a percentage, the percentage based on the incremented counter and a total number of coherence misses in the computing environment; and

determining that the percentage has reached a threshold value.

9. The computer system of claim 6, wherein the method further comprises:

determining that a reset criterion associated with the counter is satisfied;

resetting the counter based on the determining that the reset criterion is satisfied; and

placing the first cache line in the full-line coherency modebased on the determining that the reset criterion is satisfied.

10. The computer system of claim 9, wherein the reset criterion is selected from the group consisting of:

a period of time elapses;

a number of instructions complete; and

a cache line associated with the counter is cast out of the cache.

11. The computer system of claim 6, wherein the entry further associates the counter with at least one cache line adjacent to the first cache line.

12. The computer system of claim 6, wherein the entry further associates the counter with a hash value of a memory address associated with the first cache line.

13. A computer program product for cache management in a multi-processor computing environment, the computing environment including a cache configured to hold a plurality of cache lines, each cache line configurable with a coherency mode, the computer program product comprising:

a non-transitory computer readable storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method, the method comprising;

accessing a first cache linein a full-line coherency mode, wherein cache control logic associated with the cache is configured to operate or manage the first cache line in the full-line coherency mode with a full-line granularity, the accessing the first cache line resulting in a coherence request, wherein based on the accessing, incrementing a counter in an entry in a coherence miss detection table, the entry associating the counter with the first cache line;

determining that the first cache line is a high-coherence-miss cache line, wherein the determining that the first cache line is the high-coherence-miss cache line comprises determining that the incremented counter satisfies a high-coherence-miss criterion; and

based on the determining, placing the first cache line in a sub-line coherency mode, wherein the cache control logic is configured to operate or manage a plurality of sub-cache line portions of the first cache line in the sub-line coherency mode.

14. The computer program product of claim 13, wherein the method further comprises:

receiving, from another requestor in the computing environment, a request for the first cache line, the request targeting a memory address within the first cache line;

selecting a first sub-cache line portion of the first cache line, the first sub-cache line portion associated with the memory address;

notifying the requestor that only a sub-cache line portion of the first cache line will be returned; and

returning to the requestor the first sub-cache line portion in response to the request.

15. The computer program product of claim 13, wherein the first cache line is a first-cache copy of the first cache line in a first cache, and wherein a second-cache copy of the first cache line in a second cache remains in the full-line coherency mode after the placing the first-cache copy in the sub-line coherency mode.

16. The computer program product of claim 13, wherein the method further comprises:

determining that a reset criterion associated with the counter is satisfied;

resetting the counter based on the determining that the reset criterion is satisfied; and

placing the first cache line in the full-line coherency modebased on the determining that the reset criterion is satisfied.

17. The computer program product of claim 16, wherein the reset criterion is selected from the group consisting of:

a period of time elapses;

a number of instructions complete; and

a cache line associated with the counter is cast out of the cache.