Wearable device assembly with ability to mitigate data loss due to component failure

• US 9,329,993 B2
• Filed: 06/11/2014
• Issued: 05/03/2016
• Est. Priority Date: 06/12/2013
• Status: Active Grant

• Current Assignee: Nike, Inc.
• Original Assignee: Nike, Inc.
• Inventors: Zipperer, James, McKeag, Greg, Lapinsky, Mike, Haensly, Jason
• Primary Examiner(s): Nguyen, Hiep
• Application Number:
  US14/301,913
• Publication Number:
  US 20140372677A1
• Time in Patent Office: 692 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 11/142 Reconfiguring to eliminate the error group management mechanisms in a peer-to-peer network H04L67/1044
• CPC Class Codes: G06F 11/2097 maintaining the standby controller/processing unit updated initialisation or re-synchronisation thereof G06F11/1658 and subgroups
• CPC Class Codes: G06F 11/3438 monitoring of user actions tracking the activity of the user H04L67/535
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7209 Validity control, e.g. using flags, time stamps or sequence numbers
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/0634 by changing the state or mode of one or more devices
• CPC Class Codes: G06F 3/0638 Organizing or formatting or addressing of data
• CPC Class Codes: G06F 3/0647 Migration mechanisms
• CPC Class Codes: G06F 3/0685 Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays

Abstract

A wrist-worn device monitors movements of a user with a flexible circuit member. The flexible circuit member is fault tolerant. It may contain extra and/or redundant traces as well as the ability to store data on RAM if the flash memory fails or if some or all trace connections between the processor and flash memory fail. Data stored on the RAM may or may not contain less fidelity. Lower fidelity data may be used to alleviate issues arising if the RAM has less storage capacity than the flash memory.

Claims

1. A device that monitors movements of a user comprising:

a sensor configured to sense movement and generate sensor data;

a processor connected to the sensor and programmed with computer-executable instructions that, when executed by the processor, cause the device to perform the steps of;

(a) identifying when a connection to a flash memory is available;

(b) when the connection to the flash memory is available sending the sensor data to the flash memory via a first set of traces; and

(c) when the connection to the flash memory is not available, storing sensor data in a RAM of the processor.

2. The device of claim 1, wherein (c) comprises storing sensor data in the RAM of the processor at a reduced fidelity.

3. The device of claim 2, wherein the reduced fidelity is due to lower recordings per a given unit of time.

4. The device of claim 2, wherein the reduced fidelity is due to storing the data in a compressed format.

5. The device of claim 2, wherein the reduced fidelity is due to only storing predetermined types of data.

6. The device of claim 1, further comprising:

redundant traces configured to accept data from other traces in the first set of traces, if they break.

7. The device of claim 1, further comprising:

extra traces configured to be used if a given trace in the first set of traces breaks.

8. The device of claim 6, wherein the processor is further programmed and adapted to perform:

accepting, at the redundant traces, data from other traces in the first set of traces.

9. A device that monitors movements of a user comprising:

a sensor configured to sense movement and generate sensor data;

a processor connected to the sensor and programmed with computer-executable instructions that, when executed by the processor, cause the device to perform the steps of;

(a) identifying when a flash memory fails;

(b) when the flash memory has not failed sending the sensor data to the flash memory; and

(c) when the flash memory fails storing sensor data in a RAM of the processor.

10. The device of claim 9, wherein the executable instructions, when executed by the processor, further cause the device to perform the steps of:

(d) determining whether the RAM is approaching a first low capacity threshold; and

(e) in response to determining that the RAM of the processor has reached the first low capacity threshold, operating in a first operational mode wherein sensor data is stored in the RAM of the processor at a reduced fidelity.

11. The device of claim 10, wherein the reduced fidelity is due to lower recordings per a given unit of time.

12. The device of claim 10, wherein the reduced fidelity is due to only storing predetermined types of data.

13. The device of claim 10, wherein the reduced fidelity is due to storing the data in a compressed format.

14. The device of claim 10, wherein the low capacity threshold corresponds to a remaining memory capacity of the RAM of the processor.

15. The device of claim 10, wherein the executable instructions, when executed by the processor, further cause the device to perform the steps of:

(f) determining whether the RAM is approaching a second low capacity threshold; and

(g) in response to determining that the RAM of the processor has reached the second low capacity threshold, operating in a second operational mode wherein the device is configured to cease one or more data recording functions performed by the device.

16. The device of claim 15, wherein the second low capacity threshold is set at a level greater than the first low capacity threshold.

17. A device that monitors movements of a user comprising:

a sensor configured to sense movement and generate sensor data;

a flash memory;

a processor connected to the sensor and the flash memory via a first set of traces and programmed with computer-executable instructions that, when executed by the processor, cause the device to perform the steps of;

(a) identifying when at least a first trace in the first set of traces connecting the processor and the flash memory fails;

(b) when at least the first trace connecting the processor and the flash memory does not fail, transmitting data from the processor to the flash memory with a first transmission scheme; and

(c) when at least the first trace connecting the processor and the flash memory does fail, transmitting data from the processor to the flash memory with a second transmission scheme different from the first transmission scheme, wherein the transmission uses available traces in the first set of traces.

18. The device of claim 17, wherein the second transmission scheme is a time division scheme.

19. The device of claim 17, wherein the second transmission scheme is a statistical multiplexing scheme.

20. The device of claim 17, further comprising:

redundant traces configured to accept data from at least the first trace.