Multi-rate, multi-port, gigabit SERDES transceiver

• US 9,330,043 B2
• Filed: 09/09/2011
• Issued: 05/03/2016
• Est. Priority Date: 10/29/2002
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Baumer, Howard A.
• Primary Examiner(s): Pham, Chi H
• Assistant Examiner(s): Boakye, Alexander O
• Application Number:
  US13/229,150
• Publication Number:
  US 20120239846A1
• Time in Patent Office: 1,698 Days
• Field of Search: 370/247, 370/257, 370/258, 370/278, 370/282, 370/333, 370/362, 370/365, 370/366, 370/403, 370/405, 370/421, 370/460, 710/20
• US Class Current: 1/1
• CPC Class Codes: G06F 13/4027 using bus bridges G06F13/4022 takes precedence
• CPC Class Codes: H04L 43/50 Testing arrangements
• CPC Class Codes: Y04S 40/00 Systems for electrical power generation, transmission, distribution or end-user application management characterised by the use of communication or information technologies, or communication or information technology specific aspects supporting them

Abstract

A multi-port SERDES transceiver includes multiple parallel ports and serial ports, and includes the flexibility to connect any one of the parallel ports to another parallel port or to a serial port, or both. Furthermore, the multi-port transceiver chip can connect any one of serial ports to another serial port or to one of the parallel ports. The substrate layout of the multi-port SERDES transceiver chip is configured so that the parallel ports and the serial ports are on the outer perimeter of the substrate. A logic core is at the center of the substrate, where the logic core operates the serial and parallel data ports, and the bus that connects the data ports. The bus can be described as a “ring” structure (or donut “structure”) around the logic core, and is configured between the logic core and the data ports.

Claims

1. A multi-port transceiver, comprising:

a semiconductor substrate;

a plurality of ports including a plurality of serial ports and at least one parallel port, the plurality of ports being configured and arranged to be on an outer perimeter of the semiconductor substrate;

a parallel bus, arranged in a ring structure, configured to route data in a parallel format from a first port from among the plurality of ports to a second port from among the plurality of ports; and

a logic core configured to operate the parallel bus and the plurality of ports, the logic core being configured and arranged to be at an approximate center of the semiconductor substrate,

wherein the parallel bus is configured and arranged to form the ring structure around the logic core.

2. The multi-port transceiver of claim 1, wherein the first port comprises:

a serial port from among the plurality of serial ports,

wherein the second port comprises;

a parallel port from among the at least one parallel port,

wherein the serial port is configured to receive a stream of serial data and to convert the stream of serial data to a stream of parallel data, and

wherein the parallel bus is further configured to route the stream of parallel data to the parallel port.

3. The multi-port transceiver of claim 2, wherein the parallel bus is further configured to route the stream of parallel data from the serial port to one or more adjacent ports from among the plurality of ports until reaching the parallel port.

4. The multi-port transceiver of claim 1, wherein the first port comprises:

a parallel port from among the at least one parallel port,

wherein the second port comprises;

a serial port from among the plurality of serial ports,

wherein the parallel port is configured to receive a stream of parallel data,

wherein the parallel bus is further configured to route the stream of parallel data to the serial port, and

wherein the serial port is configured to convert the stream of parallel data to a stream of serial data.

5. The multi-port transceiver of claim 4, wherein the parallel bus is further configured to route the stream of parallel data from the parallel port to one or more adjacent ports from among the plurality of ports until reaching the serial port.

6. The multi-port transceiver of claim 1, further comprising:

a packet bit error rate tester (BERT) configured to provide test data to a first serial port from among the plurality of serial ports,

wherein a second serial port from among the plurality of serial ports is configured to receive the test data, and

wherein the packet BERT is configured to compare the test data and the test data as received by the second serial port to determine a bit error rate.

7. A multi-port transceiver, comprising:

a plurality of ports including a plurality of serial ports and at least one parallel port; and

a parallel bus arranged a rind to route data in a parallel format from a first port from among the plurality of ports to a second port from among the plurality of ports,

wherein the first port comprises;

a first serial port from among the plurality of serial ports,

wherein the second port comprises;

a second serial port from among the plurality of serial ports,

wherein the first serial port is configured to receive a first stream of serial data and to convert the first stream of serial data to a stream of parallel data,

wherein the parallel bus is further configured to route the stream of parallel data to the second serial port, and

wherein the second serial port is configured to convert the stream of parallel data to a second stream of serial data.

8. The multi-port transceiver of claim 7, wherein the parallel bus is further configured to route the stream of parallel data from the first serial port to one or more adjacent ports from among the plurality of ports until reaching the second serial port.

9. A multi-port transceiver, comprising:

a plurality of lines, a first set of lines from among the plurality of lines being configured and arranged to form a first port from among a plurality of ports and a second set of lines from among the plurality of lines being configured and arranged to form a second port from among the plurality of ports;

a semiconductor substrate, the plurality of ports being configured and arranged to be on a perimeter of the semiconductor substrate; and

a logic core configured to operate a parallel bus and the plurality of ports, the logic core being configured and arranged to be within the perimeter of the semiconductor substrate,

wherein the parallel bus is configured and arranged in a ring structure formed around the logic core, the parallel bus being configured to route data in a parallel format from the first port to the second port.

10. The multi-port transceiver of claim 9, wherein the plurality of lines comprises:

a plurality of differential data lines.

11. The multi-port transceiver of claim 9, wherein the first port comprises:

a first serial port from among the plurality of ports,

wherein the second port comprises;

a second serial port from among the plurality of ports,

wherein the first serial port is configured to receive a first stream of serial data and to convert the first stream serial data to a stream of parallel data,

wherein the parallel bus is further configured to route the stream of parallel data to the second serial port, and

wherein the second serial port is configured to convert the stream of parallel data to a second stream of serial data.

12. The multi-port transceiver of claim 11, wherein the parallel bus is further configured to route the stream of parallel data from the first serial port to one or more adjacent ports from among the plurality of ports until reaching the second serial port.

13. The multi-port transceiver of claim 9, wherein the first port comprises:

a serial port from among the plurality of ports,

wherein the second port comprises;

a parallel port from among the plurality of ports,

wherein the serial port is configured to receive a stream of serial data and to convert the stream of serial data to a stream of parallel data, and

wherein the parallel bus is further configured to route the stream of parallel data to the parallel port.

14. The multi-port transceiver of claim 13, wherein the parallel bus is further configured to route the stream of parallel data from the serial port to one or more adjacent ports from among the plurality of ports until reaching the parallel port.

15. The multi-port transceiver of claim 9, wherein the first port comprises:

a parallel port from among the plurality of ports,

wherein the second port comprises;

a serial port from among the plurality of serial ports,

wherein the parallel port is configured to receive a stream of parallel data,

wherein the parallel bus is further configured to route the stream of parallel data to the serial port, and

wherein the serial port is configured to convert the stream of parallel data to a stream of serial data.

16. The multi-port transceiver of claim 15, wherein the parallel bus is further configured to route the stream of parallel data from the parallel port to one or more adjacent ports from among the plurality of ports until reaching the serial port.

17. The multi-port transceiver of claim 9, further comprising:

a packet bit error rate tester (BERT) configured to provide test data to a first serial port from among the plurality of serial ports,

wherein a second serial port from among the plurality of ports is configured to receive the test data, and

wherein the packet BERT is configured to compare the test data and the test data as received by the second serial port to determine a bit error rate.

18. A method for transmitting data, comprising:

receiving a stream of serial test data by a serial port from among a plurality of ports, the plurality of ports including at least one parallel port;

converting the stream of serial test data to a stream of parallel test data;

routing the stream of parallel test data to a packet bit error rate tester (BERT); and

receiving by the packet BERT the stream of parallel test data; and

comparing in the packet BERT the stream of parallel test data and original test data to determine a bit error rate.

19. The method of claim 18, wherein routing comprises:

routing the stream of parallel test data from the serial port to one or more adjacent ports from among the plurality of ports until reaching the packet BERT.