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Multi-rate, multi-port, gigabit SERDES transceiver

  • US 9,330,043 B2
  • Filed: 09/09/2011
  • Issued: 05/03/2016
  • Est. Priority Date: 10/29/2002
  • Status: Active Grant
First Claim
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1. A multi-port transceiver, comprising:

  • a semiconductor substrate;

    a plurality of ports including a plurality of serial ports and at least one parallel port, the plurality of ports being configured and arranged to be on an outer perimeter of the semiconductor substrate;

    a parallel bus, arranged in a ring structure, configured to route data in a parallel format from a first port from among the plurality of ports to a second port from among the plurality of ports; and

    a logic core configured to operate the parallel bus and the plurality of ports, the logic core being configured and arranged to be at an approximate center of the semiconductor substrate,wherein the parallel bus is configured and arranged to form the ring structure around the logic core.

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