Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements

• US 9,330,058 B2
• Filed: 08/07/2014
• Issued: 05/03/2016
• Est. Priority Date: 11/30/2001
• Status: Expired due to Fees

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Master, Paul L., Smith, Stephen J., Watson, John
• Primary Examiner(s): Partridge, William B
• Application Number:
  US14/453,947
• Publication Number:
  US 20150039857A1
• Time in Patent Office: 635 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture
• CPC Class Codes: G06F 15/80 comprising an array of processing units with common control, e.g. single instruction multiple data processors G06F15/82 takes precedence ; for correlation function computation G06F17/15
• CPC Class Codes: G06F 7/57 Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations G06F7/49, G06F7/491 take precedence
• CPC Class Codes: G06F 9/44505 Configuring for program initiating, e.g. using registry, configuration files
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The present invention concerns configuration of a new category of integrated circuitry for adaptive computing. The various embodiments provide an executable information module for an adaptive computing engine (ACE) integrated circuit and may include configuration information, operand data, and may also include routing and power control information. The ACE IC comprises a plurality of heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability. In response to configuration information, the interconnection network is operative to configure the plurality of heterogeneous computational elements for a plurality of different functional modes.

Claims

1. A system for configuring and operating an adaptive circuit, the system comprising:

a routable and executable information module, the module having first configuration information, second configuration information, and a first routing sequence;

a plurality of heterogeneous computational elements including a first subset of the plurality of computational elements and a second subset of the plurality of computational elements designated by the first routing sequence, wherein the information module is in a format readable by each of the plurality of heterogeneous computational elements, the format including a header field having an address associated with the adaptive circuit, a routing field including at least a part of the first routing sequence, and a configuration information field including at least a part of the first configuration information;

an interconnection network coupled to the plurality of heterogeneous computational elements, the interconnection network adapted to selectively provide the first module to the plurality of heterogeneous computational elements, the interconnection network further adapted to change interconnections between the subset of the plurality of computational elements for the first functional mode in response to the first configuration information, the interconnection network further adapted to change interconnections between the subset of the plurality of computational elements for the second functional mode in response to the second configuration information; and

wherein the routable and executable information module includes timing data for the configuration and reconfiguration of the interconnections between the subset of the plurality of computational elements to perform the first and second functional modes.

2. The system of claim 1, wherein the plurality of heterogeneous computational elements are organized into a plurality of computational units.

3. The system of claim 2, wherein the plurality of computational units include a digital signal processing unit.

4. The system of claim 1, wherein the module coordinates the configuration of the subset of the plurality of computational elements for the first functional mode with operand data.

5. The system of claim 1, further comprising a memory coupled to the plurality of heterogeneous computational elements and to the interconnection network, the memory storing the first configuration information and the second configuration information.

6. The system of claim 1, wherein the first configuration information and the second configuration information are stored as a configuration of the plurality of heterogeneous computational elements.

7. The system of claim 1, wherein the first routable and executable information module is stored in a machine-readable medium.

8. The system of claim 1, wherein the first routable and executable information module is transmitted to the adaptive circuit via a wireless interface.

9. The system of claim 1, wherein the first subset of the plurality of heterogeneous computational elements are operating in the first functional mode while the second subset of the plurality of heterogeneous computational elements are being configured for the second functional mode.

10. A routable and executable information module stored in a non-transitory machine-readable medium for operating an adaptive system, the adaptive system including a plurality of heterogeneous computational elements, and an interconnection network responsive to configure interconnections between the plurality of computational elements, wherein the information module is in a format readable by each of the plurality of heterogeneous computational elements, the format including a header field having an address associated with the adaptive system, a routing field including at least a part of the first routing sequence, and a configuration information field, the module comprising:

a configuration sequence to direct a first configuration of the interconnections between at least some of the plurality of computational elements to perform a first operating mode according to a first configuration information, part of which is stored in the configuration information field, the configuration sequence further to direct a second configuration of the interconnections between at least some of the plurality of computational elements to perform a second operating mode according to a second configuration information;

a routing sequence to route information for selective routing of the configuration sequence to the interconnections between the plurality of computational elements; and

wherein the executable information module includes timing data for the configuration and reconfiguration of the computational elements to perform the first and second functional modes.

11. The module of claim 10, wherein the plurality of heterogeneous computational elements are organized into a plurality of computational units.

12. The module of claim 11, wherein the plurality of computational units include a digital signal processing unit.

13. The module of claim 10, wherein the configuration sequence of the at least some of the plurality of computational elements for the first functional mode is coordinated with corresponding operand data.

14. The module of claim 10, wherein a memory is coupled to the plurality of heterogeneous computational elements and to the interconnection network, the memory storing the first configuration information and the second configuration information.

15. The module of claim 10, wherein the first configuration information and the second configuration information are stored as a configuration of the plurality of heterogeneous computational elements.

16. A system for configuring and operating an adaptive circuit, the system comprising:

a simple computational unit having a first computational architecture including a first plurality of interconnected computational elements;

a complex computational unit having a second, different computational architecture including a second plurality of interconnected computational elements;

a first routable and executable information module, the module having first configuration information, second configuration information, and a first routing sequence designating a first and second subset of the interconnected computational elements of the computational units, wherein the first information module is in a format readable by each of the computational units, the format including a header field having an address associated with the adaptive system, a routing field including at least a part of the first routing sequence, and a configuration information field including at least a part of the first configuration information;

an interconnection network coupled to computational units, the interconnection network selectively providing the module to the computational units, the interconnection network further causing interconnections between the subset of the plurality of computational elements to be configured for performance of a first functional mode in response to the first configuration information, and the interconnection network causing the interconnections between at least some of the subset of the plurality of computational elements to be reconfigured for performance of a second functional mode in response to the second configuration information, the first functional mode being different than the second functional mode; and

wherein the first executable information module includes timing data for the configuration and reconfiguration of the computational units to perform the first and second functional modes.

17. The system of claim 16, wherein the computational elements perform at least one of the functions of memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, routing, control, input, output, and field programmability.

18. The system of claim 16, wherein the computational elements of the digital signal processing unit each perform a function from the group of multiplication, addition, subtraction, accumulation, summation and dynamic shift.

19. The system of claim 16, wherein the complex computational unit is a digital signal processing unit performing one function of the group of fixed point arithmetic functions, floating point arithmetic functions, filtering functions, and transformation functions.

20. The system of claim 16, wherein first plurality of computational elements includes a function generator and an adder, a register and an adder, a function generator and a register, or a function generator and an adder and a register, the function generator having data inputs and a control input to selection a specific function;

and

wherein the plurality of computational elements of the complex computational unit includes a multiplier and an adder, a multiplier and a register, or a multiplier and an adder and a register.