Method and device for encoding and decoding video image data

• US 9,330,060 B1
• Filed: 04/15/2004
• Issued: 05/03/2016
• Est. Priority Date: 04/15/2003
• Status: Active Grant

• Current Assignee: NVIDIA Corporation
• Original Assignee: NVIDIA Corporation
• Inventors: Tsang, Eric Kwong-Hang
• Primary Examiner(s): Werner, David N
• Application Number:
  US10/826,798
• Time in Patent Office: 4,401 Days
• Field of Search: 375/240, 375/240.01, 375/240.25, 712/10, 712/11, 712/18, 712/25
• US Class Current: 1/1
• CPC Class Codes: G06F 15/82 data or demand driven
• CPC Class Codes: H04N 19/43 Hardware specially adapted for motion estimation or compensation
• CPC Class Codes: H04N 19/436 using parallelised computational arrangements
• CPC Class Codes: H04N 19/439 using cascaded computational arrangements for performing a single operation, e.g. filtering

Abstract

A method and device for encoding and decoding video image data. An MPEG decoding and encoding process using data flow pipeline architecture implemented using complete dedicated logic is provided. A plurality of fixed-function data processors are interconnected with at least one pipelined data transmission line. At least one of the fixed-function processors performs a predefined encoding/decoding function upon receiving a set of predefined data from said transmission line. Stages of pipeline are synchronized on data without requiring a central traffic controller. This architecture provides better performance in smaller size, lower power consumption and better usage of memory bandwidth.

Claims

1. A video image data encoding/decoding device comprising:

a plurality of fixed-function data processors interconnected with at least one pipelined data transmission line wherein each of said plurality of fixed-function data processors performs a predefined encoding/decoding function upon receiving a set of predefined data from another of said plurality of fixed-function data processors,

wherein said plurality of fixed-function data processors are synchronized on data without a central controller,

wherein each of said plurality of fixed-function data processors is data driven, and each of said plurality of fixed-function data processors comprises dedicated logic that operates independently from the remaining said plurality of fixed-function data processors, and each of said plurality of fixed-function data processors comprises a first queue to queue a set of predefined data and a second queue to queue a set of predefined control data, said set of predefined data and set of predefined control data are received from a previous fixed-function data processor of said plurality of fixed-function data processors, and each of said plurality of fixed-function data processors is operable to simultaneously store a set of predefined data to a first queue of a subsequent fixed-function data processor of said plurality of fixed-function data processors and to send a set of predefined control data to a second queue of said subsequent fixed-function data processor,

wherein said first queue comprises a ping-gong buffer and said second queue comprises a ping-pong buffer.

2. The video image data encoding/decoding device of claim 1 wherein said first queue is operable for receiving a set of predefined data from said transmission line.

3. The video image data encoding/decoding device of claim 1 wherein said second queue is operable for initiating a performance of said predefined encoding/decoding function upon receiving a set of predefined control data from said transmission line.

4. The video image data encoding/decoding device of claim 1 wherein said first queue is operable for receiving a set of predefined data from said transmission line and said second queue is operable for initiating a performance of said predefined encoding/decoding function upon receiving a set of predefined control data.

5. The video image data encoding/decoding device of claim 1 wherein at least one of said plurality of fixed-function data processors comprises a bit-stream decoder.

6. The video image data encoding/decoding device of claim 5 wherein at least one of said plurality of fixed-function data processors comprises a motion compensation processor.

7. The video image data encoding/decoding device of claim 1 wherein at least one of said plurality of fixed-function data processors comprises a discrete cosine transformation (DCT) logic processor.

8. The video image data encoding/decoding device of claim 1 wherein at least one of said plurality of fixed-function data processors comprises an inverse discrete cosine transformation (IDCT) logic processor.

9. The video image data encoding/decoding device of claim 1 wherein at least one of said plurality of fixed-function data processors comprises a direction prediction processor.

10. The video image data encoding/decoding device of claim 1 wherein at least one of said plurality of fixed-function data processors comprises a de-quantization processor.

11. The video image data encoding/decoding device of claim 1 wherein at least one of said plurality of fixed-function data processors comprises an AC/DC prediction processor.

12. The video image data encoding/decoding device of claim 1 wherein at least one of said plurality of fixed-function data processors comprises a Run Level Coding (RLC) and Inverse Scan (I-Scan) logic processor.

13. The video image data encoding/decoding device of claim 1 wherein at least one of said plurality of fixed-function data processors comprises a copy and retire processor operable to combine data block matrices.

14. The video image data encoding/decoding device of claim 1 further comprising a data bus for transmitting data between said video image data encoding/decoding device and an external memory.

15. The video image data encoding/decoding device of claim 1, wherein at least one of said plurality of fixed-function data processors is powered down.

16. The video image data encoding/decoding device of claim 1, wherein at least one of said plurality of fixed-function data processors comprises a bit stream encoder processor.

17. The video image data encoding/decoding device of claim 1, wherein each of said plurality of fixed-function data processors is operable to automatically synchronize passing and buffering of data.

18. The video image data encoding/decoding device of claim 1, wherein a pipeline architecture comprises said plurality of fixed-function data processors.

19. A method for encoding/decoding video image data, said method comprising:

receiving a first set of predefined image data at a first data driven processor for performing a first predefined encoding/decoding function, wherein said set of predefined image data is queued by a first queue of said first data driven processor and wherein a first set of predefined control data associated with said first set of predefined data is queued by a second queue of said first data driven processor;

performing said first predefined encoding/decoding function via said first data driven processor; and

transmitting via said first data driven processor a second set of predefined image data to at least a second data driven processor for performing a second predefined encoding/decoding function, said second set of predefined image data is queued by a first queue of said second data driven processor, said first data driven processor and said second data driven processor are synchronized on data without a central controller, and said first data driven processor is operable to simultaneously perform said transmitting and send a second set of predefined control data to said second data driven processor, wherein said second set of predefined control data is queued by a second queue of said second data driven processor;

wherein said first queue of said first data driven processor comprises a ping-pong buffer, said second queue of said first data driven processor comprises a ping-pong buffer, said first queue of said second data driven processor comprises a ping-pong buffer, and said second queue of said second data driven processor comprises a ping-pong buffer.

20. The method as recited in claim 19 wherein said second queue of said first data driven processor is operable for initiating said performing upon receiving said first set of predefined control data.

21. The method as recited in claim 20 further comprising:

performing said second predefined encoding/decoding function via said second data driven processor, said second queue of said second data driven processor is operable for initiating said performing said second predefined encoding/decoding function upon receiving said second set of predefined control data.

22. A data encoding/decoding system comprising:

a first data driven processor operable to receive a first set of predefined image data and a first set of predefined control data from a previous data driven processor, said first data driven processor is operable to perform a first predefined encoding/decoding function, said first set of predefined image data is queued by a data buffer queue of said first data driven processor and a first set of predefined control data associated with said first set of predefined image data is queued by a control queue of said first data driven processor;

a second data driven processor connected to said first data driven processor, said second data driven processor comprises a data buffer queue and a control queue; and

wherein said first data driven processor is operable to simultaneously store a second set of predefined image data to said data buffer queue of said second data driven processor and send a second set of predefined control data to said control queue of said second data driven processor that is associated with said second set of predefined image data, said second data driven processor is operable to perform a second predefined encoding/decoding function, said first data driven processor and said second data driven processor are synchronized on data without a central controller,

wherein said data buffer queue of said first data driven processor comprises a ping-pong buffer, said control queue of said first data driven processor comprises a ping-pong buffer, said data buffer queue of said second data driven processor comprises a ping-pong buffer, and said control queue of said second data driven processor comprises a ping-pong buffer.

23. The system as recited in claim 22 wherein each of said first and second data driven processors is operable to synchronize passing and buffering of data automatically.

24. The system as recited in claim 22 further comprising a third data driven processor connected to said second data driven processor, said third data driven processor comprises a data buffer queue and a control queue, said data buffer of said third data driven processor comprises a ping-pong buffer and said control queue of said third data driven processor comprises a ping-gong buffer.