Achieving power supply and heat dissipation (cooling) in three-dimensional multilayer package

• US 9,330,213 B2
• Filed: 03/26/2013
• Issued: 05/03/2016
• Est. Priority Date: 05/21/2012
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Matsumoto, Keiji
• Primary Examiner(s): Toledo, Fernando L
• Assistant Examiner(s): Hall, Victoria K
• Application Number:
  US13/850,386
• Publication Number:
  US 20130308278A1
• Time in Patent Office: 1,134 Days
• Field of Search: 361/709, 361/710, 361714-721, 361/730, 257/690, 257/701, 257/702, 257/706, 257/707, 257/712, 257/713, 257/717, 257/720, 257/723, 257/730
• US Class Current: 1/1
• CPC Class Codes: G06F 2119/08 Thermal analysis or thermal optimisation
• CPC Class Codes: G06F 30/20 Design optimisation, verification or simulation optimisation, verification or simulation of circuit designs G06F30/30
• CPC Class Codes: G06F 30/367 Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16146 the bump connector connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/17181 On opposite sides of the body
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 2225/06565 the devices having the same size and there being no auxiliary carrier between the devices
• CPC Class Codes: H01L 2225/06589 Thermal management, e.g. cooling
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H05K 3/10 in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
• CPC Class Codes: H05K 7/205 : Heat-dissipating body thermally connected to heat generating element via thermal paths through printed circuit board [PCB] details of PCBs relating to heat transfer H05K1/0201
• CPC Class Codes: Y10T 29/49162 : by using wire as conductive path

Abstract

A computer-implemented structure for optimizing a route for power supply and heat dissipation in a multilayer chip. The method includes: setting a heat conductive thermal value for the multilayer chip by way of density, preparing a substrate that contains silicon where a wiring layer is formed facing the upper surface side of the multilayer chip, setting the power from the wiring layer of the substrate that uses silicon, manipulating the value of the power supply, and manipulating the heat conductive thermal value based on density. Both apparatuses include an organic substrate, a multilayer chip, a substrate containing silicon, a wiring layer, and a heat dissipater, wherein the components are configured to perform the steps of the above method. The method of configuring an apparatus ensures that all the multilayer chips are stored in the concave part of the organic substrate.

Claims

1. An apparatus that performs power supply and heat dissipation for a stacked multiple-chip structure from an upper surface side of said stacked multiple-chip structure, comprising:

an organic substrate provided on a lower surface side of said stacked multiple-chip structure;

a substrate that uses silicon (Si) where a wiring layer, with a thickness, is formed on a bottom surface side facing said upper surface side of said stacked multiple-chip structure;

a heat dissipater located on said substrate that uses Si that dissipates heat directly above the upper surface side of said substrate that uses Si;

said organic substrate and said wiring layer formed on said substrate that uses Si are electrically connected in a periphery of said apparatus; and

said stacked multiple-chip structure, on said upper surface side, is adapted to receive power through said wiring layer.

2. The apparatus of claim 1, wherein an initial value for said thickness of said wiring layer is between 10 μ

m and 400 μ

m.

3. The apparatus of claim 2, wherein the initial value for said thickness of said wiring layer is between 10 μ

m and 100 μ

m.

4. The apparatus of claim 3, wherein the initial value for said thickness of said wiring layer is 10 μ

m to 15 μ

m.

5. The apparatus of claim 1, wherein an electrical connection in the periphery of said apparatus is formed using a connecting body.

6. The apparatus of claim 5, wherein said connecting body comprises TAB tape.

7. The apparatus of claim 1, wherein said substrate comprises Si or SiC.

8. The apparatus of claim 1, wherein a second heat dissipater is provided on the lower surface side of said stacked multiple-chip structure in a manner to dissipate heat away from said stacked multilayer chip structure.

9. The apparatus of claim 1, wherein said organic substrate is formed with a concave part;

and

the stacked multiple-chip structure and an additional stacked multiple-chip structure are arranged so that all of said multilayer chips stacked multiple-chip structures are stored in the concave part of said organic substrate.

10. An apparatus that performs heat dissipation for a stacked multiple-chip structure from an upper surface side of said stacked multiple-chip structure, comprising:

an organic substrate provided on a lower surface side of said stacked multiple-chip structure;

a substrate that uses silicon (Si) where a wiring layer, with a thickness, is formed on a bottom surface side facing said upper surface side of said stacked multiple-chip structure;

said organic substrate and said wiring layer are electrically connected in a periphery of said apparatus; and

said stacked multiple-chip structure only receives power from said wiring layer formed on said organic substrate from said lower surface side of said stacked multiple-chip structure.

11. The apparatus of claim 10, comprising:

said organic substrate formed with a concave shape; and

the stacked multiple-chip structure and an additional stacked multiple-chip structure are arranged so that all of said stacked multiple-chip structures are stored in the concave part of said organic substrate.

12. A method of configuring an apparatus that performs power supply and heat dissipation for a stacked multiple-chip structure from an upper surface side of said stacked multiple-chip structure, comprising the steps of:

providing a heat dissipater;

preparing, on a lower surface side of said heat dissipater, a substrate that uses silicon (Si) where a wiring layer, with a thickness, is formed on a bottom surface side facing said upper surface side of said stacked multiple-chip structure;

connecting, using a thermal interface material, said heat dissipater and an upper surface side of said substrate that uses Si;

connecting said upper surface side of said stacked multiple-chip structure with said wiring layer; and

connecting an organic substrate, having a concave part, to both a lower surface side of said stacked multiple-chip structure and said wiring layer, ensuring that the stacked multiple-chip structure is stored in the concave part of said organic substrate.

13. The method of claim 12, wherein the step connecting an organic substrate to said lower surface side of said stacked multiple-chip structure and said wiring layer is performed so that joints for said lower surface side of said stacked multiple-chip structure and said wiring layer are performed by a same process using solder bump reflow.