Method and apparatus for dummy cell placement management

• US 9,330,224 B2
• Filed: 04/30/2014
• Issued: 05/03/2016
• Est. Priority Date: 04/30/2014
• Status: Active Grant

• Current Assignee: Oracle International Corporation (Oracle Corporation)
• Original Assignee: Oracle International Corporation (Oracle Corporation)
• Inventors: Ding, Duo, Sanivarapu, Srinivas, So, Lai-ching Lydia, Peters, Joseph Curt, Shisler, Carl Alfred, Fowler, Gary Lynn, Le, Thuvan, Peng, Kaiwha, Hou, Tao, Chin, Wilson Fai
• Primary Examiner(s): Kik, Phallaka
• Application Number:
  US14/266,708
• Publication Number:
  US 20150317425A1
• Time in Patent Office: 734 Days
• Field of Search: 716/112, 716/54, 716/55, 716/122, 716/123, 716/129, 716/130
• US Class Current: 1/1
• CPC Class Codes: G06F 2117/06 Spare resources, e.g. for permanent fault suppression
• CPC Class Codes: G06F 2119/18 Manufacturability analysis or optimisation for manufacturability
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36
• CPC Class Codes: Y02P 90/02 Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

Abstract

A method for manipulating a circuit design includes receiving multiple dummy cell modification parameters, selecting, by a computer processor and based on the dummy cell modification parameters, a dummy cell insertion region on a circuit design, and generating, in the dummy cell insertion region, multiple dummy cells. The method further includes selecting a first dummy cell from the dummy cells, determining, by the computer processor and based on a location of the first dummy cell, an illegal overlap with the first dummy cell, and removing, by the computer processor and from the dummy cells, the first dummy cell. The method further includes inserting, by the computer processor, on the circuit design, and after removing the first dummy cell, the dummy cells to obtain a modified circuit design, and presenting the modified circuit design.

Claims

1. A method for manipulating a circuit design comprising:

receiving a plurality of dummy cell modification parameters;

selecting, by a computer processor and based on the plurality of dummy cell modification parameters, a dummy cell insertion region on the circuit design;

generating, in the dummy cell insertion region, a plurality of dummy cells;

selecting a first dummy cell from the plurality of dummy cells;

determining, by the computer processor and based on a location of the first dummy cell, an illegal overlap with the first dummy cell;

removing, by the computer processor in response to determining the illegal overlap and from the plurality of dummy cells, the first dummy cell;

inserting, by the computer processor, on the circuit design, and after removing the first dummy cell, the plurality of dummy cells to obtain a modified circuit design; and

presenting the modified circuit design to manufacture a semiconductor wafer, wherein device degradation is reduced during manufacturing of the semiconductor wafer.

2. The method of claim 1, further comprising:

configuring, based on the location of the first dummy cell in the dummy cell insertion region, the first dummy cell.

3. The method of claim 1, wherein selecting the dummy cell insertion region comprises:

selecting a region having a device performance degradation as the dummy cell insertion region.

4. The method of claim 1, wherein selecting the dummy cell insertion region comprises:

selecting a region having a density inconsistency as the dummy cell insertion region.

5. The method of claim 1, wherein selecting the dummy cell insertion region comprises:

selecting a region having a device compatibility inconsistency as the dummy cell insertion region.

6. The method of claim 1, wherein determining, based on a location of the first dummy cell, an illegal overlap with the first dummy cell comprises:

detecting a layer-to-layer illegal overlap between the first dummy cell and a device on the circuit design.

7. The method of claim 1, wherein determining, based on a location of the first dummy cell, an illegal overlap with the first dummy cell comprises:

detecting an illegal spacing overlap between the first dummy cell and a device on the circuit design.

8. The method of claim 1, further comprising:

determining, based on a location of the first dummy cell, a device mismatch between a device on the circuit design and a second dummy cell; and

removing, in response to determining the device mismatch and from the plurality of dummy cells, the second dummy cell,

wherein the plurality of dummy cells are inserted after removing the second dummy cell.

9. The method of claim 1, further comprising:

selecting a second dummy cell to remove based on a request to remove the second dummy cell in the dummy cell modification parameter;

removing the second dummy cell from the circuit design; and

removing each connection between the second dummy cell and a device on the circuit design.

10. The method of claim 1, wherein presenting the modified circuit design comprises:

displaying a schematic of the modified circuit design; and

displaying a layout of the modified circuit design.

11. A system for manipulating a circuit design comprising:

a data repository for storing the circuit design;

a computer processor;

a dummy cell manager executing on the computer processor for causing the computer processor to;

select, based on a plurality of dummy cell modification parameters, a dummy cell insertion region on the circuit design,

generate, in the dummy cell insertion region, a plurality of dummy cells;

select a first dummy cell from the plurality of dummy cells,

determine, based on a location of the first dummy cell, an illegal overlap with the first dummy cell,

remove, in response to determining the illegal overlap and from the plurality of dummy cells, the first dummy cell, and

insert, on the circuit design and after removing the first dummy cell, the plurality of dummy cells to obtain a modified circuit design; and

a graphical user interface executing on the computer processor for causing the computer processor to;

receive the plurality of dummy cell modification parameters, and

present the modified circuit design to manufacture a semiconductor wafer, wherein device degradation is reduced during manufacturing of the semiconductor wafer.

12. The system of claim 11, wherein the data repository is further configured to store a plurality of design rules and wherein the dummy cell manager comprises a design rule enforcer configured to enforce the plurality of design rules.

13. The system of claim 12, wherein enforcing the plurality of design rules comprises:

determining the illegal overlap based on at least one design rule of the plurality of design rules, and

removing the first dummy cell based on the illegal overlap.

14. The system of claim 11, wherein the dummy cell manager comprises:

a connectivity engine configured to;

select a second dummy cell to remove based on a request to remove the second dummy cell in the dummy cell modification parameter;

remove the second dummy cell from the circuit design; and

remove each connection between the second dummy cell and a device on the circuit design.

15. The system of claim 11, wherein the graphical user interface is configured to present the modified circuit design by:

displaying a schematic of the modified circuit design, and

displaying a layout of the modified circuit design.

16. A non-transitory computer readable medium storing instructions for manipulating a circuit design, the instructions comprising functionality to:

receive a plurality of dummy cell modification parameters;

select, based on the plurality of dummy cell modification parameters, a dummy cell insertion region on the circuit design;

generate, in the dummy cell insertion region, a plurality of dummy cells;

select a first dummy cell from the plurality of dummy cells;

determine, based on a location of the first dummy cell, an illegal overlap with the first dummy cell;

remove, in response to determining the illegal overlap and from the plurality of dummy cells, the first dummy cell;

insert, on the circuit design and after removing the first dummy cell, the plurality of dummy cells to obtain a modified circuit design; and

present the modified circuit design to manufacture a semiconductor wafer, wherein device degradation is reduced during manufacturing of the semiconductor wafer.

17. The non-transitory computer readable medium of claim 16, wherein the instructions further comprise functionality to:

configure, based on the location of the first dummy cell in the dummy cell insertion region, the first dummy cell.

18. The non-transitory computer readable medium of claim 16, wherein determining, based on a location of the first dummy cell, an illegal overlap with the first dummy cell comprises:

detecting a layer-to-layer illegal overlap between the first dummy cell and a device on the circuit design.

19. The non-transitory computer readable medium of claim 16, wherein determining, based on a location of the first dummy cell, an illegal overlap with the first dummy cell comprises:

detecting an illegal spacing overlap between the first dummy cell and a device on the circuit design.

20. The non-transitory computer readable medium of claim 16, wherein the instructions further comprise functionality to:

determine, based on a location of the first dummy cell, a device mismatch between a device on the circuit design and a second dummy cell; and

remove, in response to determining the device mismatch and from the plurality of dummy cells, the second dummy cell,

wherein the plurality of dummy cells are inserted after removing the second dummy cell.