Data distribution fabric in scalable GPUs
First Claim
Patent Images
1. A processor comprising:
- a general purpose processor core;
a three-dimensional (3D) integrated circuit stack including multiple graphics processor cores, the 3D integrated circuit stack coupled to the general purpose processor core; and
interconnect logic having at least one data channel, to interconnect the graphics processor cores of the 3D integrated circuit stack and couple the graphics processor cores with a shared resource, the interconnect logic further to enable data distribution between the graphics processor cores and the shared resource over a virtual channel including multiple programmatically pre-assigned traffic classifications.
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Abstract
In on embodiment, a hybrid fabric interconnects multiple graphics processor cores within a processor. The hybrid fabric interconnect includes multiple data channels, including programmable virtual data channels. The virtual data channels carry multiple traffic classes of packet-based messages. The virtual data channels and multiple traffic classes may be assigned one of multiple priorities. The virtual data channels may be arbitrated independently. The hybrid fabric is scalable and can support multiple topologies, including multiple stacked integrated circuit topologies.
9 Citations
25 Claims
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1. A processor comprising:
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a general purpose processor core; a three-dimensional (3D) integrated circuit stack including multiple graphics processor cores, the 3D integrated circuit stack coupled to the general purpose processor core; and interconnect logic having at least one data channel, to interconnect the graphics processor cores of the 3D integrated circuit stack and couple the graphics processor cores with a shared resource, the interconnect logic further to enable data distribution between the graphics processor cores and the shared resource over a virtual channel including multiple programmatically pre-assigned traffic classifications. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A system comprising:
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a processor including a three-dimensional (3D) circuit stack including a plurality of cores, at least one of the plurality of cores including an instruction set for processing graphics instructions, the at least one core to be coupled with a shared resource on the processor via interconnect logic having at least one clock gated physical data channel and a set of virtual channels including one or more virtual channels, the one or more virtual channels having multiple programmatically pre-assigned traffic classifications; and memory coupled to the at least one core and the interconnect logic, the memory to store data for the at least one core before transmission via the interconnect logic. - View Dependent Claims (15, 16, 17, 18, 19)
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20. A non-transitory machine-readable medium having stored thereon data, which if performed by at least one machine, causes the machine to fabricate a system on a chip integrated circuit including a three-dimensional (3D) circuit stack of multiple graphics processor cores to perform a method comprising:
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determining a channel access status on a multiple node shared bus for a message from a source node to a target node, wherein at least one node of the multiple node shared bus couples with a graphics processor core of integrated circuit and at least one node of the multiple node shared bus couples with a shared resource on the integrated circuit; transmitting a message from the source node to the target node over a first data channel, wherein the message is associated with a first traffic classification having a first priority; receiving the message at a first data bus connector coupled with the graphics processor core; and based on at least the source node and the target node, switching the message from the first data channel to a second data channel. - View Dependent Claims (21, 22, 23, 24, 25)
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Specification